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Timing simulation stuck in quartus

dcyh00
Beginner
1,783 Views

When I was running a timing simulation in Quartus Prime 20.1.1.720 Lite Edition, the progress is seems like to be stuck at there and not going to move anymore, below here is the last 2 sentence in the simulation log, really appreciate for any help 

# MACRO ./Block1.do PAUSED at line 16

VSIM(paused)>

=========================================================================

For the complete log:

Determining the location of the ModelSim executable...

Using: C:\Simulation\modelsim_ase\win32aloem

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Block1 -c Block1 --vector_source="C:/Simulation/test/Waveform.vwf" --testbench_file="C:/Simulation/test/simulation/qsim/Waveform.vwf.vt"

Info: *******************************************************************

Info: Running Quartus Prime EDA Netlist Writer

Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition

Info: Copyright (C) 2020 Intel Corporation. All rights reserved.

Info: Your use of Intel Corporation's design tools, logic functions

Info: and other software and tools, and any partner logic

Info: functions, and any output files from any of the foregoing

Info: (including device programming or simulation files), and any

Info: associated documentation or information are expressly subject

Info: to the terms and conditions of the Intel Program License

Info: Subscription Agreement, the Intel Quartus Prime License Agreement,

Info: the Intel FPGA IP License Agreement, or other applicable license

Info: agreement, including, without limitation, that your use is for

Info: the sole purpose of programming logic devices manufactured by

Info: Intel and sold by Intel or its authorized distributors. Please

Info: refer to the applicable agreement for further details, at

Info: https://fpgasoftware.intel.com/eula.

Info: Processing started: Sat May 22 21:45:10 2021

Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off Block1 -c Block1 --vector_source=C:/Simulation/test/Waveform.vwf --testbench_file=C:/Simulation/test/simulation/qsim/Waveform.vwf.vt

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

 

Completed successfully.

Completed successfully.

**** Generating the timing simulation netlist ****

quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/Simulation/test/simulation/qsim/" Block1 -c Block1

Info: *******************************************************************

Info: Running Quartus Prime EDA Netlist Writer

Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition

Info: Copyright (C) 2020 Intel Corporation. All rights reserved.

Info: Your use of Intel Corporation's design tools, logic functions

Info: and other software and tools, and any partner logic

Info: functions, and any output files from any of the foregoing

Info: (including device programming or simulation files), and any

Info: associated documentation or information are expressly subject

Info: to the terms and conditions of the Intel Program License

Info: Subscription Agreement, the Intel Quartus Prime License Agreement,

Info: the Intel FPGA IP License Agreement, or other applicable license

Info: agreement, including, without limitation, that your use is for

Info: the sole purpose of programming logic devices manufactured by

Info: Intel and sold by Intel or its authorized distributors. Please

Info: refer to the applicable agreement for further details, at

Info: https://fpgasoftware.intel.com/eula.

Info: Processing started: Sat May 22 21:45:11 2021

Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory=C:/Simulation/test/simulation/qsim/ Block1 -c Block1

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Info (204018): Generated files "Block1.vo" and "Block1_v.sdo" in directory "C:/Simulation/test/simulation/qsim//" for EDA simulation tool

Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning

Info: Peak virtual memory: 4617 megabytes

Info: Processing ended: Sat May 22 21:45:11 2021

Info: Elapsed time: 00:00:00

Info: Total CPU time (on all processors): 00:00:01

 

Completed successfully.

**** Generating the ModelSim .do script ****

C:/Simulation/test/simulation/qsim/Block1.do generated.

Completed successfully.

**** Running the ModelSim simulation ****

C:/Simulation/modelsim_ase/win32aloem/vsim -c -do Block1.do

Reading C:/Simulation/modelsim_ase/tcl/vsim/pref.tcl

 

# 10.1d

 

 

# do Block1.do

# ** Warning: (vlib-34) Library already exists at "work".

#

# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012

# -- Compiling module Block1

#

# Top level modules:

# Block1

 

# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012

# -- Compiling module Block1_vlg_vec_tst

#

# Top level modules:

# Block1_vlg_vec_tst

 

# vsim -L maxv_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver -c -t 1ps -novopt work.Block1_vlg_vec_tst

 

# Loading work.Block1_vlg_vec_tst

# Loading work.Block1

# Loading maxv_ver.maxv_io

# Loading maxv_ver.maxv_lcell

# Loading maxv_ver.maxv_asynch_lcell

# Loading maxv_ver.maxv_lcell_register

# SDF 10.1d Compiler 2012.11 Nov 2 2012

#

# Loading instances from Block1_v.sdo

# Loading timing data from Block1_v.sdo

# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.

# Time: 0 ps Iteration: 0 Instance: /Block1_vlg_vec_tst File: Waveform.vwf.vt

# after#18

# Break in Module Block1_vlg_vec_tst at Waveform.vwf.vt line 51

# Stopped at Waveform.vwf.vt line 51

# Simulation Breakpoint: Break in Module Block1_vlg_vec_tst at Waveform.vwf.vt line 51

# MACRO ./Block1.do PAUSED at line 16

VSIM(paused)>

 

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2 Replies
dcyh00
Beginner
1,768 Views

Issue solved when i repeat my circuit in a new project

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RichardTanSY_Intel
1,753 Views

Hi @dcyh00 

 

Good to know that you are able to found the solution. This will be helpful to those who may come across similar issue.

With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

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