To measure internal delays in circuits

[Altera_Forum]

Hi, I want to measure the internal delay of gates using FPGA hardware and compare the propagation delays of several circuits such as ripple-carry and carry-lookahead adders.  

I want to measure the delay between the input and output pins. And also, is there some way to know about the routing delays, so that we get the actual propagation delay through the gates?

[Altera_Forum]

Why do you need to know a propogation delay through a design? you realise that this delay can vary from chip to chip, build to build and with temperature, so you wont get a very reliable measurement. 

 If you have a synchronous design you can provide timing specs to timequest and it will check to see if your design meets those specifications.

[Altera_Forum]

Hi Tricky,  

Thank you for your reply.  I am currently trying to compare the Real time performance of different kinds of high speed adders. See how they hold up against their theoretical performance. For this I will need propagation delay through my design. It is alright if it depends on other factors.  In short I need to find the time taken by the design to give my output after I give it an input.

[Altera_Forum]

You might be best doing this using time quest. Set it up with registers at the input and output of the adder then use time quest to analyse the timing. This will remove the extra delay added to route the signals in and out of the chip.

[Altera_Forum]

How about using the Quartus tools to generate a post place and route simulation netlist (ie, .vo files) and delay annotation (ie, .sdo files). 

I do this as a routine part of my flow in case I need to inspect the detailed timing behavior of some portions of the design (altho not very often any more). The 'quartus_eda' tool is used to generate this netlist, and some setup in the .qsf file as well:  set_global_assignment -name EDA_SIMULATION_TOOL "NC-Verilog (Verilog)" set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation

[Altera_Forum]

--- Quote Start ---  Hi Tricky,  Thank you for your reply.  I am currently trying to compare the Real time performance of different kinds of high speed adders. See how they hold up against their theoretical performance. For this I will need propagation delay through my design. It is alright if it depends on other factors.  In short I need to find the time taken by the design to give my output after I give it an input.  --- Quote End ---    You need a TDC to measure the tiny propagation time. Fortunately, you can implement TDC function inside older altera FPGA, for example older than CycloneIV.