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Top Level Design Error in my Verilog code

ShashwatS
Beginner
492 Views

There is a "top level design" error in my Verilog code. Please mention some instructions to resolve this issue asap.

 

 

The code is for a C element in DMRThe code is for a C element in DMR

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sstrell
Honored Contributor III
436 Views

The name you've specified as the top level entity in your Quartus project (celement) does not match the module name (c_element).

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RichardTanSY_Intel
426 Views

As sstrell mentioned, the top level entity name is mismatch with the module name.

To solve this, right-click the file and set it as Top-Level Entity.

 

Best Regards,

Richard Tan

 

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

 

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RichardTanSY_Intel
413 Views

Is the suggestion able to solve your problem?

 

Regards,

Richard Tan

 

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RichardTanSY_Intel
381 Views

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thank you.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.


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