Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Tri0 and Pulldown synthesizable in CPLDs (MAX V, MAX II, MAX7000)

CHess4
Beginner
402 Views

Hello!

I am implementing a simple bus hub design. I would like to use pulldowns for some of my inout ports. Quartus lets me compile Tri0, but gives an error when I use pulldown on the same nets - "will not synthesize". Now I am reading elsewhere that tri0 won't synthesize either.

Is there a way to implement input pull downs on Max V, Max II or Max 7000 devices?

Or where should I ask such kind of questions?

Thank you

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2 Replies
Rahul_S_Intel1
Employee
264 Views

Hi ,

There is an option for the unused pin to make it as pull up, the options available is on the Device and Pin options >> Unused pins

Rahul_S_Intel1
Employee
264 Views

Hi ,

 

 Kindly let me know if you need further assistance.

 

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