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UART core simulation

I am using Quartus Lite 20.1.1 to simulate the UART core.  I am using Nativelink to run the simulation.  There is an issue with the baud divisor in simulation.  If you select FIXED BAUDRATE in Platform Designer, the simulation accepts the write to the divisor.  If the box is left unchecked, it always loads the baud divisor from divisor_constant in the simulation code.

I have verified the baud divisor and send data at the correct baud rate to the rxd pin.  The RRDY bit never gets set.  The status register always reads 0x60 with TRDY and TMT set.

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