I am using Quartus Lite 20.1.1 to simulate the UART core. I am using Nativelink to run the simulation. There is an issue with the baud divisor in simulation. If you select FIXED BAUDRATE in Platform Designer, the simulation accepts the write to the divisor. If the box is left unchecked, it always loads the baud divisor from divisor_constant in the simulation code.
I have verified the baud divisor and send data at the correct baud rate to the rxd pin. The RRDY bit never gets set. The status register always reads 0x60 with TRDY and TMT set.
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As per discussion and some investigation, the RTL code structure of the testbenches are incorrect as not accordingly to the recommended structure.
To write a testbenches code for the avalon, would recommend to start the user guide here, which will be a great starting point. (e.g. below example can also be a great references)
Process to write a testbench to validate the behavior of the IP can be lengthy sometime.
Perhaps would suggest to system console which is a much easier, for that the example here would be a good starting point. (i.e. may refer to the 'Introduction to FPGA Simulation and Debug' workshop)