- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi I have intel pro edition and when I add my UVM test bench files and try to compile it complains as such Error(13406): Verilog HDL error at scoreboard.sv(4): object "uvm_pkg" is not declared
I am wondering if I have a syntax error when I do import uvm_pkg::*; or is uvm just not complied and available on this version quartus_pro/23.1.0.115. Please help me and provide any documentation that shows me how I can load uvm.
Thanks
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Please also provide the information needed to load and use UVM on modelsim/10.6g for future reference.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I don't know much about UVM, but why are you trying to compile testbench files in Quartus? That should be compiled in your simulation tool, Questa. The error message you mention is definitely from Quartus, not from Questa.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Oh I think I did mess up. I have only used model-sim, can you please link any documentation to a UVM example on Questa or any other example. I am not sure how to get to Questa-Sim.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
For Questasim, yes UVM is supported for Questasim 10.0a versions onwords and to imports the uvm_pkg (import uvm_pkg::*;) check this link https://community.intel.com/t5/Intel-Quartus-Prime-Software/how-to-execute-uvm-code-and-rtl-code-can-you-tell-me-the/m-p/716174, i guess you're using modelsim that's why you can't use the UVM.
For modelsim, check this link https://community.intel.com/t5/Intel-FPGA-Software-Installation/Modelsim-ASE-starter-not-directly-support-UVM/m-p/1288356
Unfortunately ModelSim does not have pre-compiled UVM features. You are probably thinking of Questa Sim.
You need to download UVM source files, you can do that here: https://www.accellera.org/downloads/standards/uvm
And you'll need to compile the uvm_pkg as well.
vlog -work work -sv -stats=none C:/work/ST/simulation/tb_captur_1.sv <uvm_pkg path>/uvm_pkg.sv +incdir+<UVM source path>/src
This is another related link https://blogs.sw.siemens.com/verificationhorizons/2011/03/08/using-the-uvm-10-release-with-questa/
If you use an earlier Questa installation, like 6.6d or 10.0, then you must supply the +incdir, and you must compile the UVM.
Thanks,
Regards,
Sheng
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
May I know does your problem being resolved?
Thanks,
Regards,
Sheng

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page