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Unable to generate HDL GHRD DE1-Soc (Quartus prime 21.1)

areebTAG
Beginner
219 Views

Hi, I wish to generate HDL for GHRD for the DE1-Soc board. 

However I get a bunch of error messages which I can't find much information online to fix. 

Upgrading the IP works fine and I've done that, so no issues there.

Please have look at my screenshot, I would be great full if someone could help. 

areebTAG_0-1649057581617.png

(The screenshot shows quartus 20.1 but I also have 21.1 installed. Someone told me 21.1 is not good and 20.1 is better for the DE1-Soc, anyway I have both installed and both give same error).

0 Kudos
5 Replies
EBERLAZARE_I_Intel
199 Views

Hi,


Can you copy the whole error message log here?


I assume you have installed WSL, but to be sure, please check if you have followed and installed all the required:

https://www.intel.com/content/www/us/en/support/programmable/articles/000074066.html




areebTAG
Beginner
190 Views

Hi,

Thnx I will have a look and get back to you with all the errors. 

areebTAG
Beginner
177 Views

areebTAG_0-1649228471836.pngareebTAG_1-1649228490561.png

I have already installed this:

https://www.intel.com/content/www/us/en/support/programmable/articles/000088789.html

Entire error script:

 

Error: 2022.04.06.07:59:11 Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Nios II Command Shell.bat requires Windows Subsystem for Linux (WSL) to run.
Error: 2022.04.06.07:59:11 Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Please install WSL and try again.
Error: 2022.04.06.07:59:11 Error: border: Error during execution of script generate_hps_sdram.tcl: seq: child process exited abnormally
Error: 2022.04.06.07:59:11 Error: border: Error during execution of script generate_hps_sdram.tcl: seq: add_fileset_file: No such file C:/Users/areeb/AppData/Local/Temp/alt9088_2269639312684602027.dir/0004_seq_gen
Error: 2022.04.06.07:59:11 Error: border: Error during execution of script generate_hps_sdram.tcl: Generation stopped, 3 or more modules remaining
Error: 2022.04.06.07:59:11 Error: border: Execution of script generate_hps_sdram.tcl failed
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:00 Info:
Error: 2022.04.06.07:59:11 Error: border: ********************************************************************************************************************
Error: 2022.04.06.07:59:11 Error: border:
Error: 2022.04.06.07:59:11 Error: border: Use qsys-generate for a simpler command-line interface for generating IP.
Error: 2022.04.06.07:59:11 Error: border:
Error: 2022.04.06.07:59:11 Error: border: Run ip-generate with switch --remove-qsys-generate-warning to prevent this notice from appearing in subsequent runs.
Error: 2022.04.06.07:59:11 Error: border:
Error: 2022.04.06.07:59:11 Error: border: ********************************************************************************************************************
Warning: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:02 Warning: Ignored parameter assignment device=5CSEMA5F31C6
Warning: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:02 Warning: Ignored parameter assignment extended_family_support=true
Warning: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:05 Warning: hps_sdram: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
Warning: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:05 Warning: hps_sdram.seq: This module has no ports or interfaces
Warning: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:05 Warning: hps_sdram.p0: p0.scc must be exported, or connected to a matching conduit.
Warning: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:05 Warning: hps_sdram.as: as.afi_init_cal_req must be exported, or connected to a matching conduit.
Warning: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:05 Warning: hps_sdram.as: as.tracking must be exported, or connected to a matching conduit.
Warning: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:05 Warning: hps_sdram.c0: c0.status must be exported, or connected to a matching conduit.
Warning: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:05 Warning: hps_sdram.p0: p0.avl must be connected to an Avalon-MM master
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:05 Info: hps_sdram: Generating altera_mem_if_hps_emif "hps_sdram" for QUARTUS_SYNTH
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:07 Info: pll: "hps_sdram" instantiated altera_mem_if_hps_pll "pll"
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:07 Info: p0: Generating clock pair generator
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:07 Info: p0: Generating hps_sdram_p0_altdqdqs
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:10 Info: p0:
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:10 Info: p0: *****************************
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:10 Info: p0:
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:10 Info: p0: Remember to run the hps_sdram_p0_pin_assignments.tcl
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:10 Info: p0: script after running Synthesis and before Fitting.
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:10 Info: p0:
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:10 Info: p0: *****************************
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:10 Info: p0:
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:10 Info: p0: "hps_sdram" instantiated altera_mem_if_ddr3_hard_phy_core "p0"
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:11 Error: seq: Nios II Command Shell.bat requires Windows Subsystem for Linux (WSL) to run.
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:11 Error: seq: Please install WSL and try again.
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:11 Error: seq: child process exited abnormally
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:11 Error: seq: add_fileset_file: No such file C:/Users/areeb/AppData/Local/Temp/alt9088_2269639312684602027.dir/0004_seq_gen
Error: 2022.04.06.07:59:11 Error: border: while executing
Error: 2022.04.06.07:59:11 Error: border: "add_fileset_file $file_name [::alt_mem_if::util::hwtcl_utils::get_file_type $file_name 0] PATH $file_pathname"
Error: 2022.04.06.07:59:11 Error: border: ("foreach" body line 4)
Error: 2022.04.06.07:59:11 Error: border: invoked from within
Error: 2022.04.06.07:59:11 Error: border: "foreach file_pathname $return_files_sw {
Error: 2022.04.06.07:59:11 Error: border: _dprint 1 "Preparing to add $file_pathname"
Error: 2022.04.06.07:59:11 Error: border: set file_name [file tail $file_pathname]
Error: 2022.04.06.07:59:11 Error: border: add_fileset_file $..."
Error: 2022.04.06.07:59:11 Error: border: (procedure "generate_sw" line 18)
Error: 2022.04.06.07:59:11 Error: border: invoked from within
Error: 2022.04.06.07:59:11 Error: border: "generate_sw $name $fileset"
Error: 2022.04.06.07:59:11 Error: border: ("if" then script line 4)
Error: 2022.04.06.07:59:11 Error: border: invoked from within
Error: 2022.04.06.07:59:11 Error: border: "if {[string compare -nocase $fileset QUARTUS_SYNTH] == 0} {
Error: 2022.04.06.07:59:11 Error: border: set top_level_file "altera_mem_if_hhp_qseq_synth_top.v"
Error: 2022.04.06.07:59:11 Error: border: add_fileset_file $top_level_fi..."
Error: 2022.04.06.07:59:11 Error: border: (procedure "generate_files" line 4)
Error: 2022.04.06.07:59:11 Error: border: invoked from within
Error: 2022.04.06.07:59:11 Error: border: "generate_files $name QUARTUS_SYNTH"
Error: 2022.04.06.07:59:11 Error: border: (procedure "generate_synth" line 3)
Error: 2022.04.06.07:59:11 Error: border: invoked from within
Error: 2022.04.06.07:59:11 Error: border: "generate_synth altera_mem_if_hhp_qseq_synth_top"
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:11 Info: seq: "hps_sdram" instantiated altera_mem_if_hhp_ddr3_qseq "seq"
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:11 Error: Generation stopped, 3 or more modules remaining
Error: 2022.04.06.07:59:11 Error: border: 2022.04.06.07:59:11 Info: hps_sdram: Done "hps_sdram" with 7 modules, 33 files
Info: 2022.04.06.07:59:11 Info: border: "hps_io" instantiated altera_interface_generator "border"
Error: 2022.04.06.07:59:11 Error: Generation stopped, 2 or more modules remaining
Info: 2022.04.06.07:59:11 Info: soc_system: Done "soc_system" with 63 modules, 119 files
Error: 2022.04.06.07:59:12 Error: qsys-generate failed with exit code 1: 70 Errors, 10 Warnings
Info: 2022.04.06.07:59:12 Info: Finished: Create HDL design files for synthesis
Info (11904): Restoring file "soc_system.BAK.qsys" to "soc_system.qsys"
Error (14923): Error upgrading Platform Designer file "soc_system.qsys"
Info (11131): Completed upgrading IP component In-System Sources and Probes with file "ip/altsource_probe/hps_reset.v"
Error (11890): Unable to automatically upgrade Platform Designer component. Please manually upgrade "soc_system.qsys" in Platform Designer
Error (23031): Evaluation of Tcl script c:/intelfpga_lite/21.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 65 errors, 32 warnings
Error: Peak virtual memory: 4878 megabytes
Error: Processing ended: Wed Apr 6 07:59:20 2022
Error: Elapsed time: 00:02:05
Error: Total CPU time (on all processors): 00:03:23

EBERLAZARE_I_Intel
153 Views

Hi,


Any update from your side?


Reply