Unable to intialize constant using data from a file(ModelSim 10.3, Quartus Prime15.1)

Altera_Forum · ‎10-13-2016

Hello, I am facing two problems with loading content from a file in VHDL. The file containts 32bit fixed point values and in each line are two values.

The whole file is about 60000 lines long. I have a package defined which has the required data types and a constant for the data.

Now when I simulate the design in ModelSim, the constant (which is an array) stays on 'U'. As I was unable to debug into the function, I tried it in Quartus, which

report Error 10536. I know what this error is about with the limitation of 10000 iterations, but I cannot understand why this applies/occurs in my case.

I call the function only once and this should be handled as part of the synthese and not realized in hardware (which is prohibited by my use of readline...).

Do someone know why this happens or what the cause is that I cannot simulate my design properly? ModelSim reports no errors and the file with the data

is placed in the major folder of the project (and accessable for ModelSim, but I guess if ModelSim would fail to open the file, it would report it).

My code:


	impure function load_table(file_name : string) return table_t is
		file handle : TEXT open READ_MODE is file_name;
		variable current_line : LINE;
		variable temp : bit_vector(63 downto 0);
		variable temp2 : std_logic_vector(63 downto 0);
		variable index_x, index_y : integer;
		variable data_int: table_t;
	begin
		index_x := 0;
		index_y := 0;
		while not endfile(handle) loop
			readline(handle, current_line);
			read(current_line, temp);
			temp2 := to_stdlogicvector(temp);
			data_int(index_x, index_y).x := signed(temp2(63 downto 32));
			data_int(index_x, index_y).y := signed(temp2(31 downto 0));
			index_x := index_x+1;
			if index_x=1280 then
				index_x := 0;
				index_y := index_y+1;
			end if;
		end loop;
		return data_int;
	end function load_table;
	constant data: table_t := load_table("data_8.txt");

Altera_Forum · ‎10-13-2016

Have you tried to debug this function? there is no error here in the code as far as I can see - does the file actually exist? does it actually get opened? what you describe could happen if the loop never runs because it cannot find the file.

Try putting some report statements in code for debug.

One a second note: quartus does not support using textio for initialising constants. So this code cannot be synthesised.

Altera_Forum · ‎10-15-2016

--- Quote Start ---

Have you tried to debug this function? there is no error here in the code as far as I can see - does the file actually exist? does it actually get opened? what you describe could happen if the loop never runs because it cannot find the file.

Try putting some report statements in code for debug.

One a second note: quartus does not support using textio for initialising constants. So this code cannot be synthesised.

--- Quote End ---

Hm, I found a problem with the array index which solved the file loading problem in ModelSim.

But that Quartus does not support textio is bad, so I will have to change my Matlab script to produce VHDL code. Are their any information available when Quartus will support textio?

Altera_Forum · ‎10-15-2016

--- Quote Start ---

Hm, I found a problem with the array index which solved the file loading problem in ModelSim.

But that Quartus does not support textio is bad, so I will have to change my Matlab script to produce VHDL code. Are their any information available when Quartus will support textio?

--- Quote End ---

No info. I requested an enhancement update in 2009 and Im still waiting. Dont expect it anytime soon, even though Xilinx have supported it for about 10 years!

You can initialise a ram with a .mif file.