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Hi all,
I've a schematic project file (fifo, AND, OR blocks etc) that I would like to simulate to verify my results. I tried using ModelSim but I can't open the schematic file with it. Did i miss something? Thanks for your help!Link Copied
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I don't think ModelSim supports schematic simulation...
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you need to convert the schematic to verilog or VHDL before you can simulate it. You can do it via the file menu:
file -> create/update -> create HDL from current file.- Mark as New
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Tried it and it worked!
Thanks alot!- Mark as New
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remember that you'll have to re-create the HDL every time you modify the schematic (and then recompile the code in modelsim).

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