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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Unable to simulate Avalon Memory-Mapped Clock Crossing Bridge Intel FPGA IP

Khai
Beginner
1,095 Views

I have a simple Platform Design QSYS system where I instantiate a "Avalon Memory Mapped Clock Crossing Bridge Intel FPGA IP" - see attachment. My design is synthesized successfully. However, when I try to compile the design with Mentor Questa, I always get this error:

# ** Error (suppressible): /storage/tools/altera/cds/212/quartus/eda/sim_lib/mentor/tennm_atoms_ncrypt.sv(40): (vopt-2732) Module parameter 'width' not found for override.

 

I cannot tell what is the root cause here because the Intel library is encrypted.

Has anyone encountered this issue before?

I am using Quartus Pro 21.2. My design is targeting Agilex FPGA device. And I'm using Mentor Questa 2021.1.

I am able to narrow down to the clock crossing bridge IP being the cause of the error but I have no idea how to fix it.

 

A quick summary of my Platform Design QSYS system: I have an Avalon Memory-Mapped master interface running at CLKA and an Avalon Memory-Mapped slave interface running at CLKB. The master interface and slave interface have different address bit-width but the same data bit-width. So in my Platform Designer QSYS, I instantiate an "Avalon Memory Mapped Pipeline Bridge Intel FPGA IP" and an "Avalon Memory Mapped Clock Crossing Bridge Intel FPGA IP". I connect the above master interface to s0 interface of the pipeline bridge IP. Then I connect the m0 of the pipeline bridge to the s0 of the clock crossing bridge. And finally, I connect the m0 of the clock crossing bridge to the above slave interface. My hope is with this QSYS, I have an Avalon addressing decoding logic that works with different clock domains.

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ShengN_Intel
Employee
1,065 Views

Hi,


Could you provide the design file with the error for further testing out?


Regards,

Sheng


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Khai
Beginner
1,022 Views

Hi Sheng,

 

Please see the attached "example.zip"

 

Thanks,

Khai

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ShengN_Intel
Employee
1,004 Views

Hi,

 

I create a simple testbench for the design you attached and I'm able to simulate the design properly with msim_setup.tcl in .../example/sim/mentor. Check out the .do file for waveform. The project file is attached below for your reference. I notice tennm_atoms_ncrypt.sv located in quartus file make sure quartus 21.2 pro is properly licensed. Or you can suppress the error by using vsim -suppress 2732. Hope it may help.

Quartus: version 21.2 Pro

Questa: starter edition 2021.2

 

*Agilex device family tested with no problem as well.

 

Best Regards

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

 

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ShengN_Intel
Employee
961 Views

Since there are no further update or concern for this thread, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you.


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