I have just debugged an issue with an AHDL design where I had unintentionally not connected a CLK to a couple of DFF registers.Apparently Quartus synthesis does not give a warning and connects the CLK input to a fixed high and later the register get removed as output assumed stuck at GND. I thought CLK was a required input for a register and would have generated a warning or error on when compile. I have verified this is not the case on Quartus versions 9.1 and 12. Why no message. If I dig into the optimization results I can see the registers were removed because of stuck clock port but this is not obvious from message window.
Yes, the warning about removal because of stuck clock is about as good as it gets.Have you tried a newer version? If you're in 9/12 are you stuck with an old device (and AHDL for that matter!)?
I thought a DFF primative in AHDL required a CLK input so was surprised that tool defaults unconnected CLK input to 1 and compiles normally.Yes I am still supporting some very old FPGA devices in legacy boards requiring Quartus 9 and using still AHDL in those cases. But going to VHDL on new designs.