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Undefined entity "altera_avalon_sc_fifo". Ensure that required library paths are specified correctly

mtinjak1
Beginner
236 Views

Hi there.

 

I have a problem using Platform designer ( Quartus Prime Lite Edition 19.1 ) to get component of altera_avalon_sc_fifo buffer-a. When I export all signals ( delete clock of platform designer, I need buffer as component), and generate VHDL code, I get error after compiling synthesis file of buffer.

I can't find library that includes altera_avalon_sc_fifo ( keep in mind 19.1 Lite edition ). I will attach image of error and .vhd file which i get from Platform designer generate option.

 

 

Thank you in forward.

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3 Replies
sstrell
Honored Contributor III
221 Views

It's not clear what you are trying to do here.  Are you trying to synthesize a component that's not connected to anything by just having the HDL file as the only file in a Quartus project?  That's not going to work.  What's your goal?

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Nurina
Employee
214 Views

Hi,


You are suppose to manually add the .qip and .sip files to your project after generating the IP core. Did you do this?


Regards,

Nurina


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Nurina
Employee
190 Views

Hi,


We do not receive any response from you on the previous question/reply/answer provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey


Regards,

Nurina


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