Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Understanding Hold Time Violaitons


I inherited a quartus design for the first time and am trying to resolve a number of timing violations.


The timing report is flagging a hold time violations in red but I'm not comprehending what exactly its telling me. Specifically the "Hold Summary" report under "Timing Analyzer".


I expect timing violations to have source clock/signal and destination clock/signal but this report only has a single column for "clock".


So what am I looking at and what am I missing?

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