Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Understanding SHA 256 verilog design

Honored Contributor II

Hello folks, I am student studying electronics. I am trying to work on verification project for SHA 256. I am very new to this filed. I am seeking help regarding SHA 256 verilog design that I got from opencores as I didn't found any documentation for the same. In general I know how SHA 256 algorithm works but in this design I am having trouble understanding how it's actually working like how are the inputs getting applied for hash computation, how busy bit is acting when on application of what cmd inputs are getting driven how read result is working. I have tried a lot to understanding but if someone can help me giving brief description about it that could be a lot helful. 

I am including link for opencores here as the design has copyright i think i wont be able to share it here but one can easily take a look at it on opencores. I will appreciate your help a lot. Thank you so much.,sha_core
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