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Understanding difference in Altera Avalon streaming & Xilinx PG156 PCI Express completion format

pdewanga
Employee
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Hi team ,

I am working on  PCI TLP Conversion from Xilinx to Altera, and require some details about the lower address of completion header format. 

In Altera Avalon streaming follows general PCI specification which has 7 bit of lower address and Xilinx address is 12 bit. Is there any functional difference for the address field between Xilinx and Altera ? If so how to map the field accurately  ?

 

Attaching the snap for TLP format for both from Xilinx and Altera PCI. 

pdewanga_0-1679912563426.png

 

 

Also the description from Xilinx PG156 document about the lower address - 

Table 3-13: Requester Completion Descriptor Fields

Bit Index Field Name Description
11:0 Lower Address This field provides the 12 least significant bits of the first byte referenced by the request. The integrated block returns this address from its Split Completion Table, where it stores the address and other parameters of all pending Non-Posted requests on the requester side. When the Completion delivered has an error, only bits [6:0] of the address should be considered valid. Note: This is a byte-level address

 

 

Regards,

Piyush

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wchiah
Employee
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Hi,

 

Thank you for reaching out.

Just to let you know that Intel has received your support request and I am assigned to work on it.

Allow me some time to look into your issue. I shall come back to you with findings.

Thank you for your patience.

 

Best regards,

Wincent_Intel


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wchiah
Employee
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Hi,


Yes, there is a functional difference in the address field between Xilinx and Altera in terms of the number of bits used for the lower address. Xilinx uses a 12-bit lower address field while Altera uses a 7-bit lower address field, both of which are compliant with the PCI specification.

When mapping the address field between Xilinx and Altera, you need to take into account the difference in the number of bits used for the lower address. For example, if you are using a Xilinx device that has a 12-bit lower address field to communicate with an Altera device that has a 7-bit lower address field, you need to shift the address bits to match the Altera device's address format.

To map the field accurately, you should consult the documentation provided by both Xilinx and Altera for their respective devices. The documentation will specify how to map the address fields between the devices and what the bit mappings should be. You may also need to consult the PCI specification to ensure that the mappings are compliant with the standard.


Hope this answer your question.

Regards,

Wincent_Intel


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pdewanga
Employee
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Hi Wincent_Intel,

Thanks for your reply. We have gone with the documents both from Xilinx and Altera, the real question is how to map this lower address. Can you briefly explain and help us with any pseudo code such that the lower address of altera is translated to Xilinx lower address?

We have gone through the document but lagging in understanding it. 

 

Regards,

Piyush

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wchiah
Employee
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Hi,


We do not have the document to translate the code from Xilinx to Altera.

But I lay down some of the suggestion for you to move on (Please noted it just example)


To translate the lower address of an Altera FPGA to an equivalent Xilinx lower address, you can use the following steps:

  1. Determine the address range of the Altera FPGA you want to translate. Let's assume it starts at address 0x00000000 and ends at address 0x0000FFFF.
  2. Determine the address range of the Xilinx FPGA you want to translate to. Let's assume it starts at address 0x80000000 and ends at address 0x8000FFFF.
  3. Calculate the offset between the two address ranges by subtracting the starting address of the Altera FPGA from the starting address of the Xilinx FPGA. In this case, the offset is 0x80000000 - 0x00000000 = 0x80000000.
  4. To translate a specific address in the Altera FPGA to an equivalent address in the Xilinx FPGA, add the offset to the address. For example, to translate address 0x00000123 in the Altera FPGA to an equivalent address in the Xilinx FPGA, you would add the offset and get 0x80000123.


Here is a simple pseudo code to perform this translation:


// Define address ranges

Altera_start = 0x00000000;

Altera_end = 0x0000FFFF;

Xilinx_start = 0x80000000;

Xilinx_end = 0x8000FFFF;


// Calculate offset

offset = Xilinx_start - Altera_start;


// Translate address

Altera_address = 0x00000123;

Xilinx_address = Altera_address + offset;


// Print translated address

print "Translated address: " + Xilinx_address;


Note that this is a simple example and the translation process may be more complex for larger address ranges or more complex FPGA architectures. User might put additional support on this. Hope this is able to help you.


Regards,

Wincent_Intel


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wchiah
Employee
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Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


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pdewanga
Employee
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Hi Wincent, 

 

Thanks for your suggestion. However, I need more understanding on this.

I am using Avalon Streaming PCIe IP with the device 1SG10MHN3F74C2LG (10M). Attaching more details of the address bus with read of length 400h. looking at the difference of Xilinx 12-bit address vs Altera 7-bit address I cannot figure it out how to decode this? 

 

pdewanga_0-1680670228211.png

 

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wchiah
Employee
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Hi,


I never compare between both Xilinx and Intel product yet.

To be honest I am not familiar with Xilinx product although we are working at same FPGA area.

However, I can lay down another suggestion for you to narrow down this issue.


To map the Xilinx 12-bit address to the Altera 7-bit address, you can follow these steps:

  1. Determine the maximum memory address that the Xilinx device can access. This information should be available in the device datasheet.
  2. Identify the memory address range that the Xilinx device is using for the read operation. This will depend on the starting address of the read operation and the length of the read.
  3. Map the Xilinx memory address range to the corresponding address range in the Altera device. This will depend on the available memory address range in the Altera device.
  4. Shift the Xilinx address to the right by 5 bits to get the equivalent 7-bit address in the Altera Avalon streaming interface.

For example, suppose that the Xilinx device can access a maximum memory address range of 4GB (2^32 bytes), and the read operation starts at address 0x80000000 and has a length of 0x400 bytes (400h bytes). To map this address range to the Altera device, you can use the following steps:

  1. Determine the maximum memory address range of the Altera device. Let's say that the Altera device can access a maximum memory address range of 1GB (2^30 bytes).
  2. Identify the memory address range that the Xilinx device is using for the read operation. In this case, the Xilinx device is reading from address 0x80000000 to address 0x80000400.
  3. Map the Xilinx memory address range to the corresponding address range in the Altera device. Since the Altera device can only access a maximum memory address range of 1GB, you can map the Xilinx memory address range to the first 1GB of the Altera memory address range. This means that the starting address of the Xilinx memory address range (0x80000000) will map to the starting address of the Altera memory address range (0x00000000).
  4. Shift the Xilinx address to the right by 5 bits to get the equivalent 7-bit address in the Altera Avalon streaming interface. In this case, the Xilinx address 0x80000000 will map to the Altera address 0x00000000, which is the starting address of the memory block in the Altera device. To get the next address in the memory block, you can increment the Altera address by 1, which will increment the Xilinx address by 32 (2^5).

I hope this helps you to understand how to map the Xilinx 12-bit address to the Altera 7-bit address. However, keep in mind that the specific mapping will depend on the memory address ranges of the Xilinx and Altera devices, and you should consult the device datasheets for more detailed information.


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wchiah
Employee
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Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


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wchiah
Employee
1,329 Views

Hi,


I am setting this as close as the discussion move to private.

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel



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