Uninferred ram due to asynchronous read logic Quartus 19.1 vs 20.1

[LehrChristoph]

Hi all,

I ran into some weird issues when I switched the projects Quartus version from 19.1 to 20.1

Using Quartus 19.1 everything worked fine, but when using 20.1 the compiler uninferes RAM Blocks due to asynchronous read logic, uses enormous amounts of logic cells and the fitting process time sky rockets from 7 seconds to over 17 minutes.

The project is written in Chisel and verilog code is generated, I use exactly the same code for both versions and I'm out of ideas what to check.

I added the logs and the generated verilog file to the attachments. I use a DE2-115 Board with a Cyclone IV FPGA, I was already pointed to this but I can't find the option in Quartus.

https://www.fpga-cores.com/instant-soc/instant-soc-on-quartus-intel-altera/

Thanks for your help

[SyafieqS]

Hi Christoph,

Few way how to handle uninfered ram in Quartus. Common way is via HDL coding style. You might need to write a code in a way Quartus infer the ram easily. Refer to link below for details.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-design-recommendations.pdf#page=44

[SyafieqS]

Hi Christopher,

May I know if there is any update?