Up-down counters

[Altera_Forum]

Hi, 

I'm new to VHDL..   i'm creating the up-down counter with async rst and a load enable signal. this load enable will determine any number within the range to be entered into the counter whereas the reset signal will reset the counter to the value of the number loaded..my problem is i didn't get the output.   my code;   library ieee;  use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt is port ( CLK,RST,LE,UD : in std_logic;  D : in std_logic_vector(3 downto 0); Q : out std_logic_vector(3 downto 0)); end cnt; architecture beh of cnt is signal Q_IN : std_logic_vector(3 downto 0);  begin Q <= Q_IN;  process( RST, CLK, LE, UD, D ) begin if RST='1' then  Q_IN <= "0000";  elsif CLK='1' and CLK'event then  --else  if LE='1' then --Q_IN <= D;  --elsif CLK='1' and CLK'event then  Q_IN <= D; if UD='1' then  Q_IN <= Q_IN + '1';  else  Q_IN <= Q_IN - '1';  end if;  end if; end if; end process; end beh;   please someone help me.   thanks.

[Altera_Forum]

Can you elaborate what you mean by "I didn't get the output". 

 process( RST, CLK, LE, UD, D ) begin if RST='1' then Q_IN <= "0000"; elsif CLK='1' and CLK'event then if LE='1' then Q_IN <= D; if UD='1' then Q_IN <= Q_IN + '1'; else Q_IN <= Q_IN - '1'; end if; end if; end if; end process;  Your "Q_IN <= D" line will never have any effect - it will always be over-ridden by the +'1' or -'1' lines.  I use numeric_std rather than std_logic_unsigned (which isn't actually an IEEE standard despite the cheeky act by the simulator companies of compiling it into the IEEE library); but try +1 and -1 rather than +'1' and -'1' - the former gives you std_logic_vector + integer, the latter gives you std_logic_vector + std_logic.  That might not make any difference - as I said I don't use that particular package.  have a think about the order of your code - I think that you might need to try:  process( RST, CLK) begin if RST='1' then Q_IN <= "0000"; elsif CLK='1' and CLK'event then if LE='1' then Q_IN <= D; elsif UD='1' then Q_IN <= Q_IN + '1'; else Q_IN <= Q_IN - '1'; end if; end if; end process;  Make sure you've got the polarity of the reset correct. Are you saying it doesn't work in simulation or on the FPGA?  It shouldn't actually affect the function but bear in mind that you only need the RST and CLK in the sensitivity list.  Hope this helps.

[Altera_Forum]

Edit: 

I wrote this post before catching up with Batfink's above post. There is plenty of similarity.    --- Quote Start ---  Hi, I'm new to VHDL..   i'm creating the up-down counter with async rst and a load enable signal. this load enable will determine any number within the range to be entered into the counter whereas the reset signal will reset the counter to the value of the number loaded..my problem is i didn't get the output.  --- Quote End ---    You should say: i'm creating the up-down counter with async rst and sync load enable signal.this load enable will determine any number within the range to be entered into the counter whereas the reset signal will reset the counter to zero.  Try this untested code:  library ieee;  use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;  entity cnt is port (  CLK : in std_logic; RST : in std_logic; LE : in std_logic; UD : in std_logic;  D : in std_logic_vector(3 downto 0);  Q : out std_logic_vector(3 downto 0) ); end cnt;   architecture beh of cnt is  signal Q_IN : unsigned(3 downto 0);   begin  Q <= std_logic_vector(Q_IN);   process( RST, CLK)  begin if RST = '1' then  Q_IN <= "0000";  elsif CLK='1' and CLK'event then  if LE = '1' then Q_IN <= D; elsif UD = '1' then  Q_IN <= Q_IN + 1;  else  Q_IN <= Q_IN - 1;  end if;  end if; end process; end beh;

[Altera_Forum]

Hi, 

I don't know how you use this code. In this way works fine!  Luca

[Altera_Forum]

Feeding U/D counter clock input from one PLL and UD input from another with no relative phase shift most likely violates setup/hold timing.