Can someone tell me is it possible to to add some small logic to an OpenCL built FPGA image after its built. Is it possible to take the openCL FPGA image and update it in any way. It would be very handy if I could use Quartus Prime to alter an OpenCL built image to make it more efficient through my own design. Is there any way to go through all the compilation flow stages individually instead of having them all done behind the scenes? Thank you.