Use BUSes with different width.

[CLa_R]

I have One BUS with 48 wire (data_out[47..0] and I would connect only two wire of this BUS to another BUS.

I make this as in picture, but I obtain an error ( Width mismatch in data_out[1..0] -- source is ""data_out[47..0]" )

How can I do it?

[sstrell]

You need to name the wires separately. Right click the bus wire from the component on the left and name it data_out[47..0] in the wire's properties. Now the name on the sliced wire, data_out[1..0], should work.