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Hi,
the Testbench Template Writer of Quartus works fine. But it just works fine if it is used inside a project.
Is there any way to generate a testbench template for just any vhdl file (without the need to create a project first) ?
Using cmd line quartus_eda cmd also asks me to pass a project...
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Hi Simon Buhrow,
Good day.
Testbenches are used for simulation purpose only not for synthesis.
Simulation can be run without creating the project but we need to provide the full relative path of the input files.
For more info refer link below on 'Design and Synthesis'.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/qts/qts_qii5v1.pdf
Thank you.
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Hi,
in the pdf I can´t find what I´m looking for.
There are a lot of information about testbenches for qsys files.
What I want to know is: Is there a way to use the Testbench Template Writer for a single source file without the need to create a project?
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Hi Simon,
Looks like Testbench Template Writer cannot be used as standalone. You still have to create project to run it because the writer takes the Netlist of the design and use it to write out the template testbench.
So we still need the Quartus Project to use the Testbench template writer.
Thank you.
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