Hi,I'm having some trouble programming my design using JTAG - specifically I cannot program my board with a time limited .SOF. I've tried this in SignalTap II firstly, which fails with "JTAG Chain Configuration: Programming failed". I figured maybe this had something to do with SignalTap II not working with time limited .sofs, so I tried programming in the Programmer, (under Finish Design in the Task window). I get similar results where I tell it to program, the dialog box comes up saying that the license is time limited, and then a notification that Progess: Failed. What am I missing? As far as I know, I should be able to program the board to use the core indefinitely, as long as the board stays tethered via jtag. I think next I will try programming using quartus_pgm.exe rather than Quartus, but if anyone could provide any insight into this problem, I would appreciate it greatly. I should note that my drivers etc all work fine, I've tested my setup with a design that does not include the Evaluation license IP, and JTAG programming that works fine. Thanks for your time - ap29
--- Quote Start --- What version of Quartus? Lite or Standard Edition? What IP is causing the issue? More info required here. --- Quote End --- Apologies for lack of info - Quartus Prime Pro 16.1 - the IP being used is the Altera/Intel Tri-speed Ethernet MAC. Here is the most recent PDF for it: https://www.altera.com/en_us/pdfs/literature/ug/ug_ethernet.pdf Thanks for taking a look
--- Quote Start --- Apologies for lack of info - Quartus Prime Pro 16.1 - the IP being used is the Altera/Intel Tri-speed Ethernet MAC. Here is the most recent PDF for it: https://www.altera.com/en_us/pdfs/literature/ug/ug_ethernet.pdf Thanks for taking a look --- Quote End --- Also, the device I'm using is an Arria 10AX115S2F45I2SGES. After attempting a configuration via cmd instead of Quartus GUI, I got error message 209014 - CONF_DONE pin failed to go high in device 1. I checked altera records for this error, and this relates to either cables being not plugged in (not applicable to my case, as I can configure just fine with a .sof that doesn't include the time-evaluation module). Other causes include a bug in Quartus versions earlier than 16.1.1 for MAX 10 chips - I am on v16.1.0 but am using an Arria10, not a MAX 10. I've checked the CONF_DONE pin for my FPGA, which is PIN_AP27, which I haven't constrained, so I don't think I'd be having an issue there either.