Using ModelSim to simulate ROM (hex file initalized)

[Altera_Forum]

Hello and thanks for the help 

 First of all I apologize because I know this is a common issue, I've spent all day today reading forum posts about simulating ROMs and various fixes, but I still can't get this to work right. A lot of solutions seem to be using some "convert_hex2ver utility that isn't even present in my quartus install.  I have a simple single port ROM in my design, and it's initialized from a hex file. If I exclude the ROM it simulates fine, when I try to simulate with the ROM, the latches that should be reading from the ROM simply read high impedance 'zzz...'  I don't get any errors indicating that modelsim is having trouble finding the hex file, no warnings at all indicating it shouldn't be working.  I'm simulating using a script that (pared down) is:  vlib work vmap work work vlog -reportprogress 300 -work work {../*.v} vsim work.Project restart -force -nowave add wave Dx1 add wave lagcounter .... ... add wave ready add wave data2 force KEY 0000 100ps force KEY 1111 200ps force KEY 0000 300ps force KEY 1111 400 ps force SW 110111111111111111 500ps force SW 111111111111111111 600ps ... force SW 111111111111111111 3800ps # Run the simulation for 4000ps run 4000ps   Any thoughts?

[Altera_Forum]

I had problems simulating with an mif file containing signed values. I switched over to Hex and it works.

[Altera_Forum]

--- Quote Start ---  I had problems simulating with an mif file containing signed values. I switched over to Hex and it works.  --- Quote End ---    Hmm I don't know, sounds like a different problem, I'm already using a hex file.

[Altera_Forum]

Any thoughts? Here is a pared down version of my code if that helps. I tried to make sure it wasn't synthesizing anything away, by tying some of the input to switches and tying output to LEDs. 

 module Project(SW, answer, LEDR, LEDG, KEY); parameter granularity = 9; input SW; input KEY; output answer; output LEDR; output LEDG; wire clock, clock1; wire result; wire data1; reg data2; wire qout reg ready; reg signed Dx1, Dy1, Dz1, Ex1, Ey1, Ez1, Fx1, Fy1, Fz1; reg signed Dx2, Dy2, Dz2, Ex2, Ey2, Ez2, Fx2, Fy2, Fz2; reg counter, lagcounter; always @(posedge clock or negedge KEY) begin //or negedge KEY if(~KEY)begin data2 <= {16{1'b0}}; Dx1 <= 3; Dy1 <= 4; Dz1 <= 1; Ex1 <= 5; Ey1 <= 3; Ez1 <= 1; Fz1 <= SW; Fx1 <= SW; Fy1 <= SW; Dx2 <= 1; Dy2 <= 1; Dz2 <= 1; Ex2 <= 2; Ey2 <= 1; Ez2 <= 10; Fx2 <= 1; Fy2 <= 2; end else begin Dx1 <= Dx2; Dy1 <= Dy2; Dz1 <= Dz2; Ex1 <= Ex2; Ey1 <= Ey2; Ez1 <= Ez2; Fx1 <= Fx2; Fy1 <= Fy2; Dx2 <= Dx1; Dy2 <= Dy1; Dz2 <= Dz1; Ex2 <= Ex1; Ey2 <= Ey1; Ez2 <= Ez1; Fx2 <= Fx1; Fy2 <= Fy1; end end always @(posedge SW) begin case(lagcounter) //0: data2 <= qout; 0: begin data2 <= qout; ready <= 0; end 1: data2 <= qout; 2: data2 <= qout; 3: data2 <= qout; 4: data2 <= qout; 5: data2 <= qout; 6: data2 <= qout; 7: data2 <= qout; 8: data2 <= qout; 9: data2 <= qout; 10: data2 <= qout; 11: data2 <= qout; 12: data2 <= qout; 13: data2 <= qout; 14: data2 <= qout; 15: ready <= 1; endcase end always @(posedge SW or negedge KEY) begin if(~KEY)begin counter <= 0; end else begin counter <= counter + 1; lagcounter <= counter; end end assign clock = SW; assign clock1 = SW; submodule test1(.Dx(Dx1), .Dy(Dy1), .Dz(Dz1), .Ex(Ex1), .Ey(Ey1), .Ez(Ez1), .Fx(Fx1), .Fy(Fy1), .Fz(Fz1), .check(result), .clock(clock), .data(data2), .loadenable(ready)); rom_mem pointdata( .address(counter), .clock(~clock1), .q(qout)); assign LEDG = (~answer) && ready; assign LEDG = result && ready; endmodule

[Altera_Forum]

The problem may be related to using a hex file. I was hinting at using a mif file with hex to see if that works instead (you could make a small mif file to begin with and just try and read a few values). I can vouch for mif files with hex values simulating while other types of file do not simulate correctly. 

 It may help you eliminate other problems from the process.

[Altera_Forum]

--- Quote Start ---  The problem may be related to using a hex file. I was hinting at using a mif file with hex to see if that works instead (you could make a small mif file to begin with and just try and read a few values). I can vouch for mif files with hex values simulating while other types of file do not simulate correctly.  It may help you eliminate other problems from the process.  --- Quote End ---    Ahh ok I see now, you're suggesting I use a mif file, but change the DATA_RADIX to hex values?

[Altera_Forum]

Yes.  

 My data vaules disappeared the other day when I used a mif file with signed values. However when I used hex value the system simulated correctly. Probably a bug, and Altera do like their bugs, so you have to find a workaround.