Version: Prime Pro 19.1
Device Stratix 10
I have *.ip files for each of the IP blocks used in my design: PLLs, Altera Clock Control, internal oscillator, ROM etc. etc.
I am trying to script a flow to generate the combined simulation compile script that I will need for the entire design.
As you mentioned , there is an option to make the simulation script from the IP, as far I know there is not generic examples or scrips to make the entire IP to make simulation