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Dear,
I haved defined a Verilog macro in the .qsf file.
But the results are far from expectations.
Is it a software bug?
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Hi MingBai,
I will look into it and will update you on this soon. Thanks.
Regards,
Pavee
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Hi,
Could you kindly explain in more detailed about your query?
Regards,
Pavee
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Hi Ming Bai,
It would be helpful if you can kindly explain further in detail about the issue.
If the issue has been resolved, kindly do let me know.
Regards,
Pavee
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We do not receive any response from you to the previous question that I have provided. This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get the support from Intel experts.
Otherwise, the community users will continue to help you on this thread.
Thank you.
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