Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

VERILOG_MACRO

MingBai
Beginner
228 Views

Dear,

 

    I haved defined a Verilog macro  in the .qsf file.

 

mingcan_2-1639620999816.png

 

But the results are far from expectations.

 

mingcan_1-1639620960860.png

 

Is it a software bug?

 

0 Kudos
4 Replies
Paveetirra_Srie
Employee
202 Views

Hi MingBai,


I will look into it and will update you on this soon. Thanks.


Regards,

Pavee


Paveetirra_Srie
Employee
169 Views

Hi,


Could you kindly explain in more detailed about your query?


Regards,

Pavee


Paveetirra_Srie
Employee
150 Views

Hi Ming Bai,


It would be helpful if you can kindly explain further in detail about the issue.

If the issue has been resolved, kindly do let me know.


Regards,

Pavee


Paveetirra_Srie
Employee
123 Views

We do not receive any response from you to the previous question that I have provided. This thread will be transitioned to community support. 

If you have a new question, feel free to open a new thread to get the support from Intel experts. 

Otherwise, the community users will continue to help you on this thread. 

Thank you.


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