VHDL 2019 Interfaces

[James_B]

I have read an earlier thread regarding VHDL 2019 and my question is different from that one. 

Actually, if there is only one feature that I would really like to see, it is interfaces. This would allow interfaces on ports and allow large VHDL designs to be compacted. 

Specifically my question is there a roadmap or timeline to release the interfaces feature of 2019 to Quartus Pro Standard? 

Thanks in advance, 

James 

[Nurina]

Hi,

The VHDL 2019 Interfaces feature is currently in the plan for Quartus Prime Pro 21.3.

There is no plan to add this feature in future versions of Quartus Prime Standard.

Regards,

Nurina

[James_B · Accepted solution]

Nurina, thanks for the feedback on the VHDL 2019 interfaces.

Well, it looks like SystemVerilog it to be used when needing or wanting interfaces in your design for Cyclone V SoC and Cyclone 10LP.

Overall I am surprised that VHDL 2019 support is not planned for Standard edition, as a device such with 110K logic elements can hold substantially large designs. 

James

[Nurina]

Hi James,

Yes, unfortunately you'll have to make do with SystemVerilog for that.

With that, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,
Nurina

P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!