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MPhil3
Beginner
599 Views

VHDL Aggregate Error

I keep getting this error, Error (10514): VHDL aggregate error : can't determine type of aggregate -- found 6 possible types

 

What should I do? Thanks!

 

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity final_game01 is

port ( enable : in std_logic;

  clk : in std_logic;

--  score0, score1 : out std_logic_vector (6 downto 0);

  LED: out std_logic_vector (8 downto 0)

  );

end entity;

architecture lab of final_game01 is

signal time_count, count, count2: integer:=0;

signal cake : std_logic;

begin

process (clk, enable)--code for FF/MOD

begin

 If (enable='1') then

  time_count<=0;

  cake<='0';

 Elsif rising_edge (clk) then

  If (time_count = 4999999) then

   cake<= NOT cake;

   time_count<=0;

  Else

   time_count<= time_count+1;--MOD count up

  End If;

 End If;

 

 If (enable='1') then--when r is 0 the count will reset at 0

   count <=0;

  Elsif (rising_edge (cake)) then

    If (count = 0) then--0

     count<=9;--9

    Else

     count<=count+1;

    

    End if;

    

    If (count2 = 0) then--0

     count2<=13;--13

    Else

     count2<=count2+1; 

    End If;

    

 End if;

 

 case (count, count2) is

  

  when (count = 0 and count2 = 0) =>

   

   LED(0)<='1';

  

  when (count = 1 and count2 = 1) =>

   

   LED(1)<='1';

   

  when (count = 2 and count2 = 2) =>

   

   LED(2)<='1';

   

  when (count = 3 and count2 = 3) =>

   

   LED(3)<='1';

   

  when (count = 4 and count2 = 4) =>

   

   LED(4)<='1';

   

  when (count = 5 and count2 = 5) =>

   

   LED(5)<='1';

   

  when (count = 6 and count2 = 6) =>

   

   LED(6)<='1';

   

  when (count = 7 and count2 = 7) =>

   

   LED(7)<='1';

   

  when (count = 8 and count2 = 8) =>

   

   LED(8)<='1';

  

 end case;

 

 End process;

End architecture;

 

 

0 Kudos
3 Replies
sstrell
Moderator
134 Views

It's hard to tell with the formatting, but you have two if statements in the process with the same if check at the same level: If (enable='1'). Perhaps one or the other of these checks should be if (enable='0').

 

I put the process in code tags to make it slightly easier to read below.

 

Also, you put enable in the sensitivity list, which makes it function as an asynchronous reset instead of an enable signal, which is usually synchronous. I don't know if that's what you're intending.

 

As far as the aggregate error is concerned, the only aggregate I see is in your case statement which doesn't look like it should be an issue. Usually the error points to a line number, so I don't know if there's other code missing here or what.

 

#iwork4intel

process (clk, enable)--code for FF/MOD  begin   If (enable='1') then   time_count<=0;   cake<='0';   Elsif rising_edge (clk) then   If (time_count = 4999999) then   cake<= NOT cake;   time_count<=0;   Else   time_count<= time_count+1;--MOD count up   End If;   End If;   If (enable='1') then--when r is 0 the count will reset at 0   count <=0;   Elsif (rising_edge (cake)) then   If (count = 0) then--0   count<=9;--9   Else   count<=count+1;   End if;    If (count2 = 0) then--0   count2<=13;--13   Else   count2<=count2+1;   End If;   End if;    case (count, count2) is   when (count = 0 and count2 = 0) =>   LED(0)<='1';   when (count = 1 and count2 = 1) =>   LED(1)<='1';   when (count = 2 and count2 = 2) =>   LED(2)<='1';   when (count = 3 and count2 = 3) =>   LED(3)<='1';   when (count = 4 and count2 = 4) =>   LED(4)<='1';   when (count = 5 and count2 = 5) =>   LED(5)<='1';   when (count = 6 and count2 = 6) =>   LED(6)<='1';   when (count = 7 and count2 = 7) =>   LED(7)<='1';   when (count = 8 and count2 = 8) =>   LED(8)<='1';   end case;   End process;

 

MPhil3
Beginner
134 Views

I am trying to make a mod 13 counter and mod 9 counter go against each other so when they both hit 2 at the same time, an LED will light up. I am programming whack a mole.

Abe
Valued Contributor II
134 Views

Try the following code and see if it works for you.

 

library IEEE; Use IEEE.Std_logic_1164.all; Use IEEE.Std_logic_unsigned.all; Use IEEE.Numeric_Std.all; Use IEEE.Std_logic_arith.all;   Entity final_game_01 Is Port( enable : In std_logic; clk : In std_logic; -- score0, score1 : out std_logic_vector (6 downto 0); LED : Out std_logic_vector (8 downto 0) ); End Entity;   Architecture RTL Of final_game_01 Is   Signal Count_M9 : std_logic_vector(3 downto 0); Signal Count_M13: std_logic_vector(3 downto 0); Begin -- Mod-9 Counter Process (clk, enable) Begin If(enable = '0') then Count_M9 <= "0000"; Elsif (enable = '1') then If (clk = '1' and clk'event) then If (Count_M9 = "1001") then Count_M9 <= "0000"; Else Count_M9 <= Count_M9 + '1'; End If; End If; End If; End Process;   -- Mod-13 Counter Process (clk, enable) Begin If(enable = '0') then Count_M13 <= "0000"; Elsif (enable = '1') then If (clk = '1' and clk'event) then If (Count_M13 = "1101") then Count_M13 <= "0000"; Else Count_M13 <= Count_M13 + '1'; End If; End If; End If; End Process;   -- Compare counters and drive LEDs   Process (Count_M9, Count_M13) Begin If (Count_M9 = "0000" and Count_M13 = "0000") then LED <= "000000001"; ElsIf (Count_M9 = "0001" and Count_M13 = "0001") then LED <= "000000010"; ElsIf (Count_M9 = "0010" and Count_M13 = "0010") then LED <= "000000100"; ElsIf (Count_M9 = "0011" and Count_M13 = "0011") then LED <= "000001000"; ElsIf (Count_M9 = "0100" and Count_M13 = "0100") then LED <= "000010000"; ElsIf (Count_M9 = "0101" and Count_M13 = "0101") then LED <= "000100000"; ElsIf (Count_M9 = "0110" and Count_M13 = "0110") then LED <= "001000000"; ElsIf (Count_M9 = "0111" and Count_M13 = "0111") then LED <= "010000000"; ElsIf (Count_M9 = "1000" and Count_M13 = "1000") then LED <= "100000000"; Else LED <= "000000000"; End If; End Process; End RTL;

It's just two counters (Mod 9 and Mod13) running in parallel and the outputs of the counters drive the LEDs as you've mentioned.