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Novice
68 Views

VHDL Configuration for TestBenches Issue

Hello,

I have a very simple entity (an AND 2 input gate) named myAnd2 with an architecture (named ex1), as top level design unit. 

I also have a testbench with two architecture (named test1, test2) , set for ModelSim-Altera simulator. 

Finally, I have a configuration declaration at the testbench file unit..

I was wonder why simulator always executes the last architecture described (named "test2") instead of executing what is indicated in the configuration declaration.

Someone of you can help me?

Thanks.

 

---------------------------------------------------------
entity TestBench is
end entity TestBench;
---------------------------------------------------------
architecture test1 of TestBench is
      component device1 is
          port (x, y : in STD_LOGIC; z: out STD_LOGIC);
      end component device1;
begin
    gateTst1: device1 port map (x => a, y => b, z => c);
      ...
end architecture test1;
---------------------------------------------------------
architecture test2 of TestBench is
      component device2 is
          port (x, y : in STD_LOGIC; z: out STD_LOGIC);
      end component device2;
begin
    gateTst2: device2 port map (x => a, y => b, z => c);
      ...
end architecture test2;
-------------------------------------------------------
configuration Tester of TestBench is
      for io
          for gateTst1 : device1
              use entity WORK.myAnd2(ex1)
              port map (x => a, y => b, z => c);
          end for;
      end for;
end configuration Tester;
---------------------------------------------------------

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3 Replies
Highlighted
Novice
66 Views

Sorry,  I did a syntax error in the previus post: the architecture in the configuration is test1.

This error was made only in writing the post, not in the running vhdl code.

-------------------------------------------------------
configuration Tester of TestBench is
      for test1
          for gateTst1 : device1
              use entity WORK.myAnd2(ex1)
              port map (x => a, y => b, z => c);
          end for;
      end for;
end configuration Tester;
---------------------------------------------------------

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Highlighted
Moderator
44 Views

Hi Emanuele,


I am not sure how did you start the simulation but, to simulate configuration, you have to start the simulation with the configuration as the top module. The simulator will load the entity/architecture pair according to the code in configuration block. Like this:


vsim work.Tester; run


Thanks,

Regards


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Highlighted
Novice
32 Views

Hi,

Thanks for the reply.

What I tried to do was to run the testbench by setting up the mytestbench.vhd file in Quartus: Setting -> Simulation -> Compile test bench ...

In this way the simulation started but ModelSim ignored the configuration declaration present in the file mytestbench.vhd; to run the simulation on the configuration I should:

1) stop the simulation that has opened

2) go to the configuration design unit, in the Library tab,

3) right-click on it and launch the simulation (it seems to me that it is also the equivalent of the command you gave me).

4) then see the signals of interest

The point is that I tried from within Quartus but I failed, as ModelSim seems to implement the default binding on the testbench it reads from Quartus anyway.

So I also tried to comment out the configuration declaration in the mytestbench.vhd file and create a new file containing only the configuration declaration, mytestconfig.vhd, (leaving untouched the mytestbench.vhd file in the same folder), and thus put the file mytestconfig.vhd in Quartus: Setting -> Simulation -> Compile test bench ...

However, when running the simulation, the simulator gave me an error.

It seems that in order to simulate a configuration you have to do it from ModelSim, as indicated previously.

I wonder if, acting from inside Quartus, it is possible to choose the configuration to simulate.

Thank you.

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