VHDL Generator

[Altera_Forum]

Hello i've written a VHDL generator in Python ( https://github.com/andrecp/vhdl_gen ), feel free to use and give feedback! 

The idea is to generate the entity,architecture and signals from a simple .txt file. It's very boring to type everything in VHDL from this simple .txt https://github.com/andrecp/vhdl_gen/blob/master/blink_led.txt with 8 lines you can generate a full VHDL design with 74 lines.  A splitted state machine (combinational/sequential) is used.  Please read the README before using, also i have a portuguese VHDL blog if anyone wants to read ( www.andrecastelan.com.br) Cheers!

[Altera_Forum]

I like MyHDL (http://www.myhdl.org) personally. The author gives a good argument for it here (http://www.programmableplanet.com/author.asp?section_id=2438&doc_id=250236). His most recent company also produced a good VHDL-specific ide (http://www.sigasi.com/). 

 Different purpose (and target audience), I know, but I thought I'd post this nonetheless.  Cheers,  slacker

[Altera_Forum]

These tools are all fine as experimental tools, and Im sure work fine for smaller projects. 

But I really dont see how they scale, without adding an extra level of complexity to an already large project. (ie. another tool to have to learn to use).   Unless they get some sort of mainstream support and use, I cant really see them catching on.

[Altera_Forum]

Hehe i don't know about MyHDL but my project aims to be really simple, i was going to make it do more things but then i realized that it would just add extra complexity and i wouldn't use it. The way it is today i just use it to generate my new designs and save me the time to type all the ports, library declarations, process declarations and regs <= next. 

 Cheers