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The VHDL IEEE 1076-2019 was released late last year. One of its feature are "Conditional analysis tool directives" that make it possible for us to check what tool is analysing the code when it is executed.
I have found that Microsemi Libero's synthesis tool Synopsys Synplify ME version P-2019.03M-SP1-1, January 2020 that comes with Libero 12.4 has the "Conditional analysis tool directives" within it. This can be seen inside the release notes of Synplify ME.
How far is Altera from incorporating this features into their program and also what about ModelSim?
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Hi,
The VHDL-19 "Conditional analysis tool directives" currently planned to incorporate in Quartus next year. (subject to change).
Please allow me to close the case for now and you are welcome to reply/tag my name here or open a new case if you would like to get an update on this feature.
Best Regards,
Shyan Yew
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Hi,
Unfortunately, I have no knowledge of this but I will consult with our internal team.
Please allow us some time to check on this.
Thanks.
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When inferior programs like Synplify and ActiveHDL can have this feature introduced into them this year, it does not make sense why the posh ones like Quartus and ModelSim do not even plan to introduce them in. This is my conclusion based on what I have discovered so far.
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Unfortunately, the VHDL-19 "Conditional analysis tool directives" is not incorporated in Quartus tool currently.
The good news is we have a plan to support Vhdl-19, we are working with them to add conditional analysis tool directive" in our tool as well. Though we can not provide you an ETA, rest assured that our engineering team shall definitely work on this.
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Hi,
The VHDL-19 "Conditional analysis tool directives" currently planned to incorporate in Quartus next year. (subject to change).
Please allow me to close the case for now and you are welcome to reply/tag my name here or open a new case if you would like to get an update on this feature.
Best Regards,
Shyan Yew
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We are in the year 2021 now. Is there a plan to incorporate any feature of IEEE 1076-2019 into Quartus now?
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If you are refer to "conditional analysis tool directive" then yes, it is currently in plan for Quartus Pro 21.3 but it might subject to change.
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Intel taking a long time and then only to introduce this feature into the Pro version and not standard version is quite cruel. Here is an idea, how about Intel not spend anytime at all in introducing VHDL 2019 into their Quartus Prime and spend their resource elsewhere that will objectively make them more money?
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Sorry if it caused any inconvenience to you or your team due to the delay. Our engineering is working closely with the language provider to implement this feature in our Quartus tool.
Sorry that I do not know that you would like this to be implement this in the Quartus Standard initially. Usually the engineering team will implement the new feature in the Quartus Pro first before implement it to the Quartus Standard. I don't see any reason why this feature can't be implemented in Quartus Standard but I will confirm this with the team.
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I have confirm with the engineering team. Sorry to say that the feature would not be implemented in the Quartus standard due to the source code in the Quartus Standard is outdated. Due to resource constraint, we are not able to develop the new features in that code.
The new feature will only be implemented in Quartus Pro version.
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Things like this do not make complete sense. People that do not need to use latest Stratix and Arria will not want to pay extra for the Quartus Pro. It does not support older devices anyway.
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I don't think Intel plans to add earlier Cyclone (II-V), Max (II-V) or Arria (II-V) into Quartus Pro over their product life cycle. Is that true?
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Yes, there is currently no plan to add Cyclone (II-V), Max (II-V) or Arria (II-V) into Quartus Pro version.
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Hi,
The engineering team reviewed the LRM and found the description is lacking for this feature.
Could you help to share some examples which may clarify their doubts?
Some real life examples might help them to clear those doubts.
Best Regards,
Shyan Yew (Richard)
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I have attached a screenshot. It is from section 24.2 of the LRM IEEE Std 1076-2019.
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