VHDL Syntheis Problem with Quartus -II 64 : RISING_EDGE ,ERROR :10822,10028,10029

[Altera_Forum]

Hi Friends,

I am trying to implement a communication protocol in FPGA with VHDL. I am using Qaurtus-II 64 for logic synthesis. As a part of my implementation I had to implement a state machine for the channel coding of the protocol. The waveform has strict timing constraints , that it the reason I decided to code it in a finite state machine which cycles it state to get the requried waveform pattern.

Now here comes the problem, I successfully compiled the below code in ModelSIM simulator, but unfortunately it shows up some errors in during synthesis. I am not an experienced programmer in VHDL. any help from you guys would be really appreciable. The below are the code and the error details. I could not attach the complete code here, I removed some irrelevant part. The complete code in the attachment.

END ARCHITECTURE;

Synthesis Error:

-----------------------

Error (10822): HDL error at codec_ch_coding_CHA_src.vhd(83): couldn't implement registers for assignments on this clock edge

Error (10822): HDL error at codec_ch_coding_CHA_src.vhd(97): couldn't implement registers for assignments on this clock edge

Error (10822): HDL error at codec_ch_coding_CHA_src.vhd(111): couldn't implement registers for assignments on this clock edge

Error (10822): HDL error at codec_ch_coding_CHA_src.vhd(140): couldn't implement registers for assignments on this clock edge

Error (10822): HDL error at codec_ch_coding_CHA_src.vhd(162): couldn't implement registers for assignments on this clock edge

Error (10822): HDL error at codec_ch_coding_CHA_src.vhd(173): couldn't implement registers for assignments on this clock edge

Error (10028): Can't resolve multiple constant drivers for net "TMP_MINISLOTACTPNT_SET" at codec_ch_coding_CHA_src.vhd(220)

Error (10029): Constant driver at codec_ch_coding_CHA_src.vhd(65)

Error (12153): Can't elaborate top-level user hierarchy

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 9 errors, 42 warnings

Error: Peak virtual memory: 1156 megabytes

Error: Processing ended: Thu Sep 10 10:21:41 2015

Error: Elapsed time: 00:00:09

Error: Total CPU time (on all processors): 00:00:20

Error (293001): Quartus II Full Compilation was unsuccessful. 11 errors, 42 warnings

Thanks in advance!

[Altera_Forum]

Synthesis requires that if you want to use clock edge assignment then do it at start of process. You may do that after reset statement but otherwise it is strictly the very start.