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Altera_Forum
Honored Contributor I
783 Views

VHDL code works when compiled on Quartus Prime V15.1 but breaks on V17.1

Hello, 

I have code working on a hardware design that was compiled using Quartus Prime version 15.1. I installed QP version 17.1 and compiled the same code but the code did not work as expected. I have an IO port that was not being used (pins were assigned in top level entity) and added IO port code to help debug and recompiled in 17.1 and it seems to have "fixed" the code (very strange). "ioout" is the port I added and used in the attached code. 

I am not sure if it is an issue with the code or a compiler issue. Both compiler versions were used with default settings. 

Any help with understanding the compiler settings would be appreciated.
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Altera_Forum
Honored Contributor I
30 Views

Sorry I cannot help you, byt can you edit your post so the opening code tag is after your text and before the actual code? That 'll show the red text you mention as well as make the code more readible. Maybe you could also remove the many <br> tags?

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