VHDL code

[Altera_Forum]

Hello Guys 

I got this Code  library ieee; use ieee.std_logic_1164.all;  entity NewLUT is port (  clk : in std_logic;   --encoder_a : in std_logic;  data_in : in integer range 3185 to 4215 ; --std_logic_vector(12 downto 0);  data_out : out std_logic_vector (30 downto 0);   out_ready : out std_logic  ); end; architecture arc_NewLUT of NewLUT is signal temp : std_logic;   begin   process  begin  if CLK'EVENT and CLK = '1' then  temp <= '1';  if temp = '1' then  case data_in is  when 3185=> data_out <= ("1010101101110111011101110111100");   when 3186=> data_out <= ("1010101101101001110100000011011");  when 3187=> data_out <= ("1010101101011100001010001111011");  when 3188=> data_out <= ("1010101101001110100000011011010");  when 3189=> data_out <= ("1010101101000000110110100111010");  when 3190=> data_out <= ("1010101100110011001100110011001");  when 3191=> data_out <= ("1010101100100101100010111111001");  when 3192=> data_out <= ("1010101100010111111001001011001");  when 3193=> data_out <= ("1010101100001010001111010111000");  when 3194=> data_out <= ("1010101011111100100101100011000");  when 3195=> data_out <= ("1010101011101110111011101110111");  when 3196=> data_out <= ("1010101011100001010001111010111");  when 3197=> data_out <= ("1010101011010011101000000110110");  when 3198=> data_out <= ("1010101011000101111110010010110");  when 3199=> data_out <= ("1010101010111000010100011110110");  when 3200=> data_out <= ("1010101010101010101010101010101");  when 3201=> data_out <= ("1010101010011101000000110110101");  when 3202=> data_out <= ("1010101010001111010111000010100");  when 3203=> data_out <= ("1010101010000001101101001110100");  when 3204=> data_out <= ("1010101001110100000011011010011");   when 3205=> data_out <= ("1010101001100110011001100110011");  when 3206=> data_out <= ("1010101001011000101111110010011");  when 3207=> data_out <= ("1010101001001011000101111110010");  when 3208=> data_out <= ("1010101000111101011100001010010");  when 3209=> data_out <= ("1010101000101111110010010110001");  when 3210=> data_out <= ("1010101000100010001000100010001");  when 3211=> data_out <= ("1010101000010100011110101110000");  when 3212=> data_out <= ("1010101000000110110100111010000");  when 3213=> data_out <= ("1010100111111001001011000110000");  when 3214=> data_out <= ("1010100111101011100001010001111");  when 3215=> data_out <= ("1010100111011101110111011101111");  when others => data_out <= ("1111111111111111111111111111111");  end case;  else  data_out <= ("0000000000000000000000000000000");  end if;  out_ready <= '1';  wait for 25 ns; -- ERROR  out_ready <= '0';   end if;    --  -- Add a flag to be used as a clk to the register  --  end process; end arc_NewLUT ;    the error msg is : error (10533): vhdl wait statement error at newlut.vhd(75): wait statement must contain condition clause with until keyword. Why is this error i did not want UNTIL all i need to wait for 25 ns evrey time the code uses the case statement.

[Altera_Forum]

I think that wait for x ns in uncorrectly (the time is specified only in the testbench) 

in my opinion, you can bind the time at the clock time with a variable, for example   if clock'event and clock = 1 count = count +1;  if (count = 25)  out_ready = 1  ---operation----  out_ready = 0   and after that in the testbench you specified the clock time...example 10 ns and so your out_ready change every 25*10 ns...  I think that this is the only thing that you can do...  i hope that my suggest is useful...:)   Stefania

[Altera_Forum]

But i do not want to wait for 25 clk events, i just want to wait for 25ns (this time to load the number in the case statement to the output) every time i enter the case statement and this for to be sure that i did not enter the case statement twice before i load the preview number

[Altera_Forum]

Things happen concurrently in VHDL when executed. Create a counter based off of an available clock, when it hits x number of clock cycles that adds up to 25ns pull an enable high. Recommend to try and simulate to see if you get the intended result.

[Altera_Forum]

for what I know about... 

wait for x ns isn't possible in vhdl...but i think that is strange that you have need exactly 25 ns..if you want to do an hysteresis there are other methods...  bye Stefania:)

[Altera_Forum]

This falls into the difference between C code and HDL.  

   Starting near the top of the process you have: temp <= '1';  temp is a signal, not a variable(which is good. I advise using signals as much as possible as it is closest to hardware). The only place is gets assigned a value is in this one line. There is no conditional on this, so it will basically power up to 1. (It could power up to 0 and go to 1 on the first clock of the design, but I don't believe that is your intent). Next you have the case statement which looks good(I'm not following what you're doing with the integer range, but assume it is necessary. Note that most HDL does not use integer ranges like this...).  Finally, at the end is:  out_ready <= '1';  wait for 25 ns; -- ERROR  out_ready <= '0';  Not that all signal updates in a process occur concurrently, i.e. at the same time. You're telling out_ready to get a '1' and a '0' at the same time. The wait for 25ns is purely a simulation symantic. The FPGA has no internal sense of time. It doesn't know what 25ns, as you're providing the clock and it could be any frequency(timing analysis can probably be looked at later). Most people are suggesting you build a counter(although 25ns) is pretty quick. So if you're clock period is 5ns, which is a relatively fast 5ns period , then you would decode when this has counted to 5 and send an output signal to tell out_ready that it can change. Even if synthesis could infer a counter out of this, there are many things it would miss. Would you want an asynchronous output on the counter? Do you want it to count to 4(20ns) and then send a signal so it can be evaluated on the next clock cycle, at time 25ns. Etc.  This is where you need to understand the target technology, which is LUTs(combinatorial logic), registers, RAMs and in some parts DSP blocks. Most of your code will target the first two. Think of HDL as a low-level description of logic and registers, and remember that registers all occur concurrently, i.e. they can toggle on every clock cycle unless you explicitly tell them not to. To be honest, in learning an HDL I would get a book that shows schematics with every example. I feel that's the best way to get started and learn how what you write translates into the FPGA. Good HDL designers understand the logic they're targeting and mentally have a good image of what their code will map to. If you write HDL from a more algorithmic standpoint(i.e. I know what I want done, but have no idea how it will get synthesized), you can write some good-looking code that gives horrible results.

[Altera_Forum]

Hello, 

 wait for "time" is not a synthesizable statement. There is no kind of Hardware wich would support this. I agree to the others here: If you need the 25 ns timing you can use a enable signal wich is derived from a clock which runs at 40 Mhz and enable the output for one clock cylce.  When I look at your code, I've got one questions to you and the community, which is a little bit off topic: In the case statement you use large bit vectors in binary coding. when 3186=> data_out <= ("1010101101101001110100000011011"); I would use internally a 32 bit vector and code the output vector in this way    . . . signal data_internal : std_logic_vector(31 downto 0); begin   process  begin  if CLK'EVENT and CLK = '1' then . . . case... . . . when 3186=> data_internal <= x"55B4E81B" . . . end case; . . . end process;  data_out <= data_internal(30 downto 0);  end arch..;  I think this version has a better "readabiltiy". What do you think? What do the others in here think about this?  Regards Christian

[Altera_Forum]

One last thing about the wait for 'time' function is that it doesn't fit into the FPGA view. In generally, you want everything moving as fast as possible. So you usually want a decode value available on the next clock edge, for every clock edge(I'm ignoring multicycle cases). So expect it to always be there, decoded on the next edge. Time shouldn't play much into your coding at first(there often are higher level time issues, like I need the data through the chip in 1us, and I have a latency of 40 clocks, and the clock is running at 100MHz, so... but that's a much higher analysis and often not necessary. 

 Whether to use data_internal versus data_out is purely a preference. I actually like the first case better since I don't like I having too many lines that don't do anything, as it can add clutter. The big benefit of what you're doing is that you can use data_internal elsewhere inside the code, while data_out can only go off chip since it's type OUT. (You could make it type BUFFER, which would solve that problem)  As for how to write up the decode, that's usually a function of how the decode is being written. Maybe it's a look-up table in a data sheet of another part, where it's written as 1's and 0's. Maybe it's the output of a Perl of C script to do a cosine table(which this clearly is not), which might do binary, but might do ASCII. Maybe it's a Matlab output. But with large/complex decodes, there's usually a 'source' that prescribes the syntax, and with HDL you usually have enough flexibility to do whatever that source outputs.

[Altera_Forum]

Hi, 

thanks for your reply. OK i agree, this isn't the best example and it depends on your source, but personally i like the "Hex" values. A lot of C-Code in our company uses hex-values so its much easier to read for the C-programmers here. ;) (When you have to exchange "tables" between C and VHDL). But a few months ago I had to review such a handcoded LUT with 32 Bit wide vectors, and it was no fun to find the typos...:eek:   Christian

[Altera_Forum]

Thanks u all this is really helped me, bu now i have the question, how can i make a delay in VHDL ?

[Altera_Forum]

the instruction for delay is AFTER 

 a <= b nor c after 1ns  i hope that this is a solution for your problem  Bye Stefania:)

[Altera_Forum]

Amirster, can you take a step back and explain what you're trying to do? In the original code you had a wait of 25ns. Synthesizable VHDL doesn't have a strong concept of time. The suggestions of making a counter depend on your clock frequency, which is outside of the VHDL construct. For example, if you made a counter that waits for 5 cycles, that will be different if you feed a 10MHz clock into the system versus a 100MHz clock. 

If you're looking for pure delay(and no registers), that is strongly recommended agains. There are cases where people do it, but it requires min/max setup and hold timing analysis, and can be quite complicated. I think we can answer your question better if you describe your problem from a higher level, as you most likely don't want a pure delay.

[Altera_Forum]

The first step is to have some kind of clock, a couple of time higher then the requested time intervals. What I usually do is make the design synchroneous to a masterclock. 

You can evaluate "on rising edge". I am used to the old AHDL language of Altera ( early user, late adapter....) it will look like:  DFF.clk := Global clock ; evaluate every clock pulse DFF.d := Data == Value ; Latch result Result := DFF.q ; DFF2.clk := Global clock ; DFF2.d := Result ; Result2 := DFF2.q ; Delaye with one clock pulse  eg in hardware you are creating a delay pipeline.  Other solutions are start a counter and gate the result at a certain clock count, Use shift registers ( which are in fact cascaded DFF's )  While writing VDL, just think in hardware!  Succes,  Andries