VHDL inout port in gate-level simulation always get Undefined State

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VHDL inout port in gate-level simulation always get Undefined State

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I have exactly the same issue as 2017 post

<https://forums.intel.com/s/question/0D70P000005tksYSAQ/vhdl-inout-port-in-gatelevel-simulation?language=en_US>

I'm using Quartus Prime Lite 19.1 (latest version), looks this problem has not been addressed until today. This issue cause all the design with Data bus implementation design verification failed, it is a big issue I think.

The root cause actually has been found, in Quartus generated .VHO object INOUT port has been changed to be BUFFER port for some reason, and BUFFER doesn't accept 'Z' assignment.

Anyone know how to work around with this issue?

Thanks,

Jeremy

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