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Altera_Forum
Honored Contributor I
828 Views

VHDL "Quantum" bug

Hi all, 

 

I hope nobody has written about this before. I took a look but I found nothing... 

 

I'm a VHDL newbie and I'm facing an issue which is driving me crazy. The thing is that I have designed and implemented a VHDL component, pretty complex if I may say. I coded the RTL model, I refactorized and optimized the code and I checked the RTL netlist to check that it matches with my design. Everything OK. The simulation works as expected too. 

 

The problem comes when I synthetise the design for my DE0 NANO board. I can see that the design works but some parts don't work as expected. There's clearly a bug. After checking all my code, I found nothing so I just added some out ports to the entity to check them with a logic analyser. Those ports add no logic. I just map some internal signals to them to try to monitor what's going on. 

 

However, once I map those signals, everything works as expected. No bugs. Nothing. If I remove the debug ports, the problem appears again. 

 

I don't think this is a speed problem as the maximum frequency I'm using is 1MHz. I also checked all the code and I optimised it for synthesis. I can see using Quartus rtl map viewer that no extra logic is added. 

 

Any clue of what can be hapening? Why there's no bug if I add debuging ports to my entity whilst the design doesn't work well if I remove those ports? 

 

Thanks a lot in advance. 

 

Cheers, 

Javier
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4 Replies
Altera_Forum
Honored Contributor I
48 Views

This sounds like some sort of timing problem - changing the output will change the fit seed and re-route the design, which may now mean that a route that previously failed is a different length that now works. 

Do you have timing constraints for the design? How are you using a 1MHz clock? is it logic generated? these are notorious for creating timing problems. Have you synchronised all asynchronous inputs properly?
Altera_Forum
Honored Contributor I
48 Views

Hi Tricky, 

 

Sorry for my delayed reply and thank you very much for your reply to my questions. 

 

Actually I considered to add timimg constraints to my design but as the frequency is relatively "low" I thought that it may not be worthy. I certainly was wrong so I will start reading about TimeQuest, timing constraints and SDC in order to learn and apply it to my design. 

 

One more question if I may: Another problem that I had (which clearly seems to be the same) is that some register loopbacks that I had on my design didn't work even when the simulation was perfect. I read, I guess in Quartus Handbook, that register loopbacks should be avoided so I added an extra register on the loopback path and an extra clock cycle and then everything worked out. So I would like to know if this register loopback issue could be fixed with timing constraints as well or if I should keep the registers that I placed on the loopback path. 

 

Sorry for all the questions but I still have a lot to learn here :) 

 

Thanks for your time in advance. 

 

Regards, 

Javier
Altera_Forum
Honored Contributor I
48 Views

Not quite sure what you mean by "register loopback"? did you mean logic loops? logic loops are certainly a problem and can only be fixed by removing them.

Altera_Forum
Honored Contributor I
48 Views

Yep, That's it. 

 

Thanks, 

Javier
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