VSIM 3033 (MODELSIM ALTERA) ERROR FFT IP CORE

[ICace]

Hello,

I'm trying to simulate the FFT IP Core block with ModelSim-Altera.

I have generated the testbench with the IP parameter Editor and I'm getting this error when I run the RTL Simulation:

What can I do?

** Error: (vsim-3033) c:/intelfpga/17.1/quartus/bin64/db/ip/bloquefft/submodules/bloquefft_fft_ii_0.sv(59): Instantiation of 'asj_fft_si_se_so_bb' failed. The design unit was not found.

#  Time: 0 ps Iteration: 0 Instance: /bloquefft_tb/bloquefft_inst/fft_ii_0 File: c:/intelfpga/17.1/quartus/bin64/db/ip/bloquefft/submodules/bloquefft_fft_ii_0.sv

#     Searched libraries:

#       C:/intelFPGA/17.1/modelsim_ase/altera/vhdl/altera

#       C:/intelFPGA/17.1/modelsim_ase/altera/vhdl/220model

#       C:/intelFPGA/17.1/modelsim_ase/altera/vhdl/sgate

#       C:/intelFPGA/17.1/modelsim_ase/altera/vhdl/altera_mf

#       C:/intelFPGA/17.1/modelsim_ase/altera/vhdl/altera_lnsim

#       C:/intelFPGA/17.1/modelsim_ase/altera/vhdl/cyclonev

#       C:/intelFPGA/17.1/quartus/bin64/simulation/modelsim/rtl_work

#       C:/intelFPGA/17.1/quartus/bin64/simulation/modelsim/bloqueFFT

#       C:/intelFPGA/17.1/quartus/bin64/simulation/modelsim/bloqueFFT

# ** Warning: (vsim-3473) Component instance "bloquefft_inst_clk_bfm : altera_avalon_clock_source" is not bound.

#  Time: 0 ps Iteration: 0 Instance: /bloquefft_tb File: C:/intelFPGA/17.1/quartus/bin64/bloqueFFT/testbench/bloqueFFT_tb/simulation/bloqueFFT_tb.vhd

# ** Warning: (vsim-3473) Component instance "bloquefft_inst_rst_bfm : altera_avalon_reset_source" is not bound.

#  Time: 0 ps Iteration: 0 Instance: /bloquefft_tb File: C:/intelFPGA/17.1/quartus/bin64/bloqueFFT/testbench/bloqueFFT_tb/simulation/bloqueFFT_tb.vhd

# ** Warning: (vsim-3473) Component instance "bloquefft_inst_sink_bfm : altera_conduit_bfm" is not bound.

#  Time: 0 ps Iteration: 0 Instance: /bloquefft_tb File: C:/intelFPGA/17.1/quartus/bin64/bloqueFFT/testbench/bloqueFFT_tb/simulation/bloqueFFT_tb.vhd

# ** Warning: (vsim-3473) Component instance "bloquefft_inst_source_bfm : altera_conduit_bfm_0002" is not bound.

#  Time: 0 ps Iteration: 0 Instance: /bloquefft_tb File: C:/intelFPGA/17.1/quartus/bin64/bloqueFFT/testbench/bloqueFFT_tb/simulation/bloqueFFT_tb.vhd

# Error loading design

# Error: Error loading design

#    Pausing macro execution

# MACRO ./fft_on_top_run_msim_rtl_vhdl.do PAUSED at line 17

[SyafieqS]

Hi Ignacio,

You can refer to this link as it same issue. You can execute manually "Generate Simulator Script for IP" in Quartus, end then run the script in Modelsim.

[1] https://forums.intel.com/s/question/0D50P00003yyO6LSAU/fft-ip-core-and-modelsim (FFT IP Core and Modelsim)

[2]https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20093.pdf (Generate Simulator Script for IP)

Thanks,

Regards.

[ICace]

Hello, thank you for your answer.

I have checked the post you have sent me up, but I'm working with Quartus Prime Standard and it hasn't the tool "Generate Simulator Script for IP" and also Quartus pro has no support for my FPGA, Cyclone V gx starter kit.