Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Verifying final channel depth

Altera_Forum
Honored Contributor II
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Is there a way to verify the final, post compiled, depth of a channel. I have a design that requires a deep fifo, critical for maximizing throughput performance. I want to verify that the compiler has in fact set the depth to what I've set using the depth parameter. Am I safe to assume that the implemented channel will never be less than the specified depth.

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Altera_Forum
Honored Contributor II
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Is there a way to verify the final, post compiled, depth of a channel. I have a design that requires a deep fifo, critical for maximizing throughput performance. I want to verify that the compiler has in fact set the depth to what I've set using the depth parameter. Am I safe to assume that the implemented channel will never be less than the specified depth. 

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The implemented channel depth is shown in the "source view" tab of the area report. It is always equal or larger than the depth that is set by the user in the kernel.
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