Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15475 Discussions

Verifying final channel depth

Altera_Forum
Honored Contributor II
768 Views

Is there a way to verify the final, post compiled, depth of a channel. I have a design that requires a deep fifo, critical for maximizing throughput performance. I want to verify that the compiler has in fact set the depth to what I've set using the depth parameter. Am I safe to assume that the implemented channel will never be less than the specified depth.

0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
77 Views

 

--- Quote Start ---  

Is there a way to verify the final, post compiled, depth of a channel. I have a design that requires a deep fifo, critical for maximizing throughput performance. I want to verify that the compiler has in fact set the depth to what I've set using the depth parameter. Am I safe to assume that the implemented channel will never be less than the specified depth. 

--- Quote End ---  

 

 

The implemented channel depth is shown in the "source view" tab of the area report. It is always equal or larger than the depth that is set by the user in the kernel.
Reply