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Altera_Forum
Honored Contributor I
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Verilog Coding

The following Verilog code is used to realize the SVPWM technique.The code has 5 modules.The module "sect_det" when run shows the output "sd" same for all clock cycles though it has inputs that vary with every clock cycle. I am unable to identify the bug.Please help me with the same. Also, the code needs to be optimized. Suggestions are welcomed. 

Verilog Code is attached. 

 

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