Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Verilog Coding

Altera_Forum
Honored Contributor II
1,040 Views

Hello, 

 

I'm getting the following error when I'm implementing the below Verilog code. 

 

[Synth 8-403] loop limit (65536) exceeded 

 

parameter N=10; 

parameter M=8; 

parameter depth=(1<<N); 

 

 

reg [M-1:0]stack_mem[depth-1:0]; 

 

 

always@(posedge clk) 

begin 

if (rst==1'b1) 

begin 

next_sp=0; 

dataout=0; 

for(i=0;i<(depth-1);i=i+1) 

begin 

stack_mem[i]=0; 

end 

end 

end 

 

 

Here "For loop" has to increase only up to 1023 but again why I'm getting loop limit exceeded error? 

 

Can anyone help me out? 

 

Thanks in advance. 

0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
263 Views

Where is i declared? Probably should be declared as an integer

 

Probably like this, with the added text in red: 

 

always@(posedge clk) begin : block_name integer i; if (rst==1'b1) begin next_sp=0; dataout=0; for(i=0;i<(depth-1);i=i+1) begin stack_mem=0; end end end 

 

Note that by requiring that clearing the whole memory in one clock cycle be done, you will be forcing the implementation of stack_mem[] to be done be an array of clearable registers, and not using a block_ram type of memory structure. Hope that is what you intend. 

 

Also clk, rst, next_sp, and dataout need to be declared somewhere (maybe you left out some code ... ?)
Altera_Forum
Honored Contributor II
263 Views

Thanks for your response. It's my mistake.i declared "i" as a single bit.

Reply