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Valued Contributor III
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Verilog $display(" ") equivalent/does not compile in VHDL ?

Hello, 

 

I have been looking for the equivalent of the $display("") command in VHDL for some time now: 

 

main_clock: process  

 

begin 

 

CLK_CPU<='1'; 

 

wait for TClock/2; 

 

$display("test "); --error  

 

CLK_CPU<='0'; 

 

wait for TClock/2; 

 

end process; 

 

 

 

What ever i do the lines above do not compile. (see bold)  

 

** Error: C:/FpgaProjects/Q17/DE2_115_Shark_Serial_Component/main_bench.vhd(33): near "$": syntax error 

 

 

Should i include a library or is there a modelsim setting i need to change ? 

Lots of documents are available about the different possible parameters and Modelsim tutorials, 

the answer to this rather basic question i could not find. 

 

Thanks for any help, 

 

Johi.
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3 Replies
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Valued Contributor III
65 Views

There are really two answers to this. You can either use the report statement: 

 

report "test"; 

 

or you can use the textio library.  

 

use std.textio.all; .... write(OUTPUT, "test" & LF); -- test and line-feed  

 

OUTPUT is a built in file that is the system console. There are many tutorials out there on how to use textio. 

 

VHDL does not have equivolents of the Verilog System Calls (that start with $).
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Valued Contributor III
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You cannot use Verilog/SV system tasks in VHDL. Both are different languages. In VHDL you can use the write () function to write values to console during simulation. Use the IEEE textio package and then call the write ( ) function. 

 

Use Std.textio.all; .. .. write ( ) ; -- write values to display
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Valued Contributor III
65 Views

Hello Tricky & eapenabrm, 

 

Tanks for the answer, I read about write & textio, thought this was reserved for disk file io. 

Never thought about the OUTPUT stream. 

 

Best Regards, 

Johi.
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