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15548 Discussions

Verilog if statement with a signed signal

AndyN
New Contributor I
1,299 Views

This feels like it should be a stupid question but does quartus do something strange when compiling if statements using signed signals? As an example, I have some code in the following form:

 

typedef logic signed [ 3:0] Int4_t;

Int4_t testValue;

...

if (testValue <= 0)

//Do the negative branch

else

//Do the positive branch

 

Modelsim behaves as I'd expect with this but then the design behaves as if the testValue is always unsigned in hardware so does the wrong thing. Obviously the work around is to just manually do a check of bit 3 but this seems like a weird behaviour to me...

 

Thanks,

Andy

 

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1 Solution
AndyN
New Contributor I
268 Views

So after digging through the LRM, it looks like Quartus is actually doing the correct thing per the spec (however I maintain that Modelsim is doing the correct thing per common sense). File it away as a nasty gotcha I guess....

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7 Replies
AndyN
New Contributor I
268 Views

Oh, should also say (in case it makes a difference) that this is Quartus Prime Pro 16.1, compiling for SystemVerilog, running on Windows 10.

 

Andy

Tricky
New Contributor II
268 Views

With only a snippet, cant really comment.

Can you post more code?

Abe
Valued Contributor II
268 Views

That may be coz you've used integer values in the if statement. When you use integers, Quartus will treat it as unsigned 32 bit integers during synthesis and truncate the unused bits. I say try specifying the bit values in the if condition

 

if ( signal < 4'b0000)

 

else

 

...

 

Using the signed values for comparison will or should yield the correct results.

AndyN
New Contributor I
268 Views

I'm not sure that that would help though - my understanding was that int 0 is effectively the same as 32'd0, no? So surely a comparison to 0 or a comparison to 4'b0000 would behave in the same way?

bitwise
New Contributor I
268 Views

​Try this:

module test ( input signed [3:0] a, output eq, output gt, output lt ); localparam x = 4'sb1101; // neg 3 assign eq = (a == x) ? 1'b1:1'b0; assign gt = (a > x) ? 1'b1:1'b0; assign lt = (a < x) ? 1'b1:1'b0; endmodule

 

AndyN
New Contributor I
268 Views

Just to be clear - I'm really not actually looking for a fix to the code (I've done that by just manually doing a check on the sign bit). I'm just very confused why the Quartus compiler is doing something fundamentally different than the Modelsim compiler. Obviously one of them is doing the correct thing and the other isn't....

AndyN
New Contributor I
269 Views

So after digging through the LRM, it looks like Quartus is actually doing the correct thing per the spec (however I maintain that Modelsim is doing the correct thing per common sense). File it away as a nasty gotcha I guess....

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