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Very long compilation time / Advanced physical optimization. Quartus Prime. Cyclone V

Altera_Forum
Honored Contributor II
3,020 Views

Dear all, 

 

I am a new user of Altera, Quartus and Cyclone V. We have a (preliminary) design that I finally managed to compile in about 3 hours. About the half of the Cyclone V (5CEBA9F31C8) is used. The first point is that the fitter stayed a very long time at 36% completed, after the log "Info (14951): The Fitter is using Advanced Physical Optimization." For that reason I had to turn off this optimization to have a chance to compile. When I turn on the "Advanced Physical Optimization", the overall compilation last more than 8 hours. 

 

I just installed Quartus Prime Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition. I have an Intel Core i5-4460 CPU @ 3.2 GHz running Windows 7 Pro SP1 with 8 Gb RAM. According to Altera recommendations, the RAM should be (just) sufficient. And according to Process Explorer the RAM is not the problem. I let Quartus use as many cores as possible (even if I found some post in the forum stating that it might be a problem...) 

 

We are at a preliminary stage of the design (and I am discovering Quartus), so I did not enter physical constraints (pin) nor timing constraints. Will it speed up the compilation? I do not think so! 

 

Thank you
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5 Replies
Altera_Forum
Honored Contributor II
724 Views

Without any timing constraints, it will assume you want an FMax of 1000 Mhz, and may try rather hard.  

Set up timing contraints for your design may make it's life easier.
Altera_Forum
Honored Contributor II
724 Views

 

--- Quote Start ---  

Without any timing constraints, it will assume you want an FMax of 1000 Mhz, and may try rather hard.  

Set up timing contraints for your design may make it's life easier. 

--- Quote End ---  

 

 

Thank you Tricky! 

 

Indeed, in the mean time I added some timing constraints (not all, for now) and the compilation is quite faster. My first goal was only to see if the design could fit in the FPGA (the board is not yet designed, we could still chose another FPGA...), so my project is not complete.
Altera_Forum
Honored Contributor II
724 Views

Yes the progress bar doesn't move a lot when the fitter is running. It isn't stalled but it's doing a lot of work. There isn't really a point in turning on the optimizations before you set up timing constraints imho. 

If you have some parts of the design that don't have high timing requirements, or work on a slow clock, it can be a good idea to put your timing constraints now. By default the fitter will try to make everything as fast as possible (iirc the default clock frequency for the constraints when you haven't specified anything is 1GHz), and if you have slow signals putting correct timing constraints can help the fitter concentrate on other parts of the design and it *may* make your project compile faster. But this of course depends a lot on your actual design. At least define all your clock frequencies, and check in the timequest report that they have been interpreted correctly. 

Do you have big combinatorial chains in your design, or anything that can make it hard for the fitter?
Altera_Forum
Honored Contributor II
724 Views

Today I encountered the same problem, but I solved it with this method. 

https://www.alteraforum.com/forum/showthread.php?t=50702
SparkyNZ
New Contributor II
96 Views
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