Vhdl code

[Altera_Forum]

Hello 

I have a code in VHDL that have 2 processes. what will happend when i run the code ? I mean which process will be executed first ? or they are gonna executeed at the same time or what will happen? For example I have this code --  library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;  entity counter16step is port (  reset,  clk_in : in std_logic;  number_clk : in std_logic_vector (23 downto 0);  p_n : out std_logic ); end;  architecture arc_counter16step of counter16step is  signal cntr_devider : std_logic_vector (23 downto 0);  signal flag_p_n : std_logic; begin  process (clk_in, reset) begin  if reset = '1' then  cntr_devider <= "000000000000000000000000";  elsif rising_edge (clk_in) then  if flag_p_n = '1' then  cntr_devider <= cntr_devider + 1;  end if;  end if; end process;  process (clk_in, reset) begin  if reset = '1' then  flag_p_n <= '1';  elsif falling_edge (clk_in) then  if cntr_devider = number_clk then  flag_p_n <= '0';  else  flag_p_n <= '1';  end if;  end if; end process;  p_n <= flag_p_n;  end;  what will happend here ? which process will run first ?

[Altera_Forum]

They will run concurrently. 

 That is the beauty of VHDL abd Verilog.

[Altera_Forum]

The simulator will schedule the process or called it event in simulator to run those to run at simulation time X. They are meant to be run concurrently in the hardware. However if you think of it, microprocess can only run one instruction for a time. So it depends on the simulators. Simulator Z may run proceses A first while simulator Y run process B first if you look from the CPU point of view. But from the simulation point of view, these proceses will be scheduled to be run at the same simulation time X. This is my understand. Hope it is clear. :)

[Altera_Forum]

Yes,  

 From simulator point of view they will run concurrently but u must look from the target device perspective and then see how it goes . Imagine ur real time environment that which all events are likely from power on to steady state. and how they are going to be scheduled and later must also cater for unlikely conditions where u may not realize but ur code may end up like unknown states and as u have the same sensitivity list for two processes try to combine them in one and u will see that the sequence would itself be sorted out. And in hierarchy when its sorted out for high level designer it trickles down to hard ware implementation level accordingly.  THX

[Altera_Forum]

It may be obvious to all, or it may be the jist of the question. When the assignments in the process that uses a clock edge are assigned, they take their next value after the clock edge. So, there is no pass through effect, such as if you use variable assignments. From the simulator's point of view, when the statement is parsed, the assignment's new value to push from the right hand side to the left hand side is scheduled to occur later, even if only time X plus "delta" later.  

 So, it doesn't matter which process is evaluated first. Concurent is good. Which is why you never assign a signal in two different processes.

[Altera_Forum]

Thanks you all guys :)

[Altera_Forum]

yours process in currently done at the same time. 

if you want manage yours operation with a clock, I suggest you the instruction "clk'event"  if clk' event and clk = 1  so you can reduce lines of code.  smile Stefania