Viewing Submodule Inputs and Outputs without assigning to Top Level Outputs?

[Altera_Forum]

Hi All, 

 I've been taking some courses over the past few months that have used Quartus II heavily. One thing I never understood was how I can view the state of internal wires within a module and present it in the waveform simulation.  It is a real pain (and usually error prone) to declare secondary outputs for each signal that I then connect by hand.  Is there a way to streamline this process and get accurate readings without duplicating every single signal?  Thanks for any tips.

[Altera_Forum]

With simulation in modelsim, you have access to all internal signals as written in your RTL. If you are using schematic drawings, you need to first convert them to HDL for simulation.