Hi,
I got a warning in my module.
Warning (10230): Verilog HDL assignment warning at OFDM_demod_block.v(274): truncated value with size 21 to match size of target (11)
This warning is shown in the below line of the verilog code .
rd_addr_cp_data <= timing_offset - r_no_of_addr_subtract;
where
timing_offset--> timing offset[20:0] coming from another module.
rd_addr_cp_data --> read address of a 2 port ram used to store the input data coming from previous module
Here rd_addr_cp_data is of 11 bits , r_no_of_addr_subtract of 16 bits and timing_offset is of 21 bits. That's why they are showing warning. So if i change the depth in order to change the address bit width to 21, the max depth that the RAM support is 16384 (which is 2^14).
And also the depth shouldn't be changed as per design (currently it is 2048).
The max value of timing_offset is 160*7680-1( it is a 21 bit value).
That is, in order to clear the warning, I can't change the left hand side and right hand side bit widths of the equation.
So is there any other way to remove this warning?
Best regards,
Elizabeth
