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Altera_Forum
Honored Contributor I
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Warning (14320): Synthesized away node -> what does it mean?

Hi All, 

 

I'm receiving the following warning message during the Analysis and Elaboration stage:Warning (14320): Synthesized away node "fpga_top:lfpga_top_inst|bit_mgr_wrp:bit_mgr_inst|bit_mgr:i_bit_mgr|fifo_top:i_fifo|fifo_sup:i_fifo_sup|dcfifo:dcfifo_component|dcfifo_r6m1:auto_generated|altsyncram_iea1:fifo_ram|q_b" 

 

What does it mean? Is this OK to receive such warning? It actually points to the output port of RAM (which is a part of the FIFO IP).  

 

Should I worry about this warning?  

 

How can I locate this node in the Quartus Netlist (Graphic Viewer)? I want to see where the node is connected to. 

 

How can I report the floating (not connected) ports? 

 

Can I receive a description of the warning from inside of Quartus (from TCL Console)? How? Is there a Manual/UserGuide for Quartus warnings/errors/etc?  

 

 

Thank you!
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2 Replies
Altera_Forum
Honored Contributor I
1,039 Views

If it got synthesised away, it means the synthesis tool determined that the node has no effect on any outputs, so has removed it from the design. This often occurs to unconnected nets, nets that are stuck low or high, registers not connected to a clock (or the clock is stuck at 1/0), registers with enable always low or registers with reset always asserted. If you were not expecting this, you will need to review the warnings and code to determine why the node was removed. 

 

Receiving the warning is ok, if you are expecting it. Many designers use the fact above to have parts of the design deliberately removed by leaving ports disconected, or generics set in such a way that only uses part of a design.  

 

The nets will no longer exist if they have been removed. They may exist on the RTL viewer, but wont exists on the mapped view and wont exist in the final design.
Altera_Forum
Honored Contributor I
1,039 Views

I have been receiving the following warnings when I generate an Altera PLL: 

 

Warning (14284): Synthesized away the following node(s): 

Warning (14285): Synthesized away the following PLL node(s): 

Warning (14320): Synthesized away node "PLL_Main:PLL_inst|PLL_Main_0002:pll_main_inst|altera_pll:altera_pll_i|outclk_wire[2]" 

Warning (14284): Synthesized away the following node(s): 

Warning (14285): Synthesized away the following PLL node(s): 

Warning (14320): Synthesized away node "PLL_Main:PLL_inst|PLL_Main_0002:pll_main_inst|altera_pll:altera_pll_i|outclk_wire[1]" 

 

 

All the output clocks get synthesized away, except for one. I have triple checked that all the output clocks (I tried with 2, 3, 4 clocks at different times) ARE connected to modules which do get synthesized. Further, I get the following clock created, no idea from where: 

 

PLL_Main:PLL_inst|PLL_Main_0002:pll_main_inst|altera_pll:altera_pll_i|fboutclk_wire[0] 

 

I have not had this problem in the past, where I used the PLL Megafunction to generate clocks. I am currently using Quartus 17.1 . Do any specific constraints need to be added in the SDC file to circumvent this? 

 

Thanks
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