Warning (18390): Intel FPGA IP Evaluation Mode (Simulation-Only) feature is turned on

[BDarji]

Dear all,

We would like to share something here. We hope it would be helpful someone in future.

Quartus Prime Version 19.1.0 Build 240 03/26/2019 Patches 0.02 SJ Pro Edition
FPGA Family: Cyclone 10 GX

In our design, we were using one encrypted IP core in evaluation mode. We had an evaluation license for that IP core. We had that IP core added in Platform Designer (formerly Qsys) system. You would be aware that Quartus Prime Pro generates .ip files for all components added in Platform Designer and those .ip files shall be added in Quartus project. Hence, we added those .ip files in Quartus project. Due to the evaluation license, Quartus was generating time limited programming file. This was as expected. So far, so good!

Issue:
For some debugging purpose, we commented out Qsys design instance from our top module. But we didn't remove .ip files related to this. With this, Quartus was unable to generate programming file and assembler report was showing following warnings:

Warning (115003): Can't generate programming files for your current project because you do not have a valid license for the following IP core or cores.
Warning (115005): Unlicensed IP: XXXX
Warning (115005): Unlicensed IP: "Nios II Embedded Processor Encrypted output(6AF7 00A2)"

Quartus synthesis report was showing following warnings:
Warning (18390): Intel FPGA IP Evaluation Mode (Simulation-Only) feature is turned on for all cores in the design
Warning (18394): Some cores in this design do not support the Intel FPGA IP Evaluation Mode feature
Warning (18395): "XXXX" does not support the Intel FPGA IP Evaluation Mode feature
Warning (18395): "Nios II Embedded Processor Encrypted output" does not support the Intel FPGA IP Evaluation Mode feature

This was strange as we already have evaluation license for that IP core and infact Quartus was showing that license in license menu.

Work-around:
We found out that if we remove encrypted IP core from design, we shall also remove its corresponding .ip files from Quartus project file list. With that, we were able to generate programming file again.

Thank you,
Bhaumik

[sstrell]

Your work-around is the normal mode of operation.  You shouldn't have to ever add the .ip files from a Platform Designer design to your Quartus project.  When you create the .qsys file, you have to associate the .qsys to your project .qpf file.  That's all you have to do.  Everything else is handled for you file-wise in Pro.

[BDarji]

Hello,

Thank you for your quick response.

I will try this and share feedback. 

Kind Regards,

Bhaumik

[BDarji]

Hello,

I noticed that when we create new Qsys system and generates its HDL files in Quartus Prime Pro, .ip files alongwith .qsys are automatically added under file set. Is this expected behaviour?

Thank you,
Bhaumik

[sstrell]

Yes.

[BDarji · Accepted solution]

Hello,

Thanks again for quick response.

Here is the conclusion:
If you are using evaluation license of some IP core being used in Qsys system and if you have disabled part from where that Qsys system is instantiated, you should remove .qsys as well as related .ip files from Quartus project file set to generate programming file.

Merry Christmas in advance! Enjoy Festive Season!

Cheers,
Bhaumik