Warnings 18390 and 18395 for Quartus Prime Pro

[BDarji]

Hello,

Let me start with some background information to give better idea about issue.

Background:

Quartus Prime Version 19.1.0 Build 240 03/26/2019 Patches 0.02 SJ Pro Edition
FPGA Family: Cyclone 10 GX

We had one Quartus design in which we were using Platform Designer system.

There were following components in our design:

• Nios II CPU - Encrypted form
• On-chip memory
• System ID
• JTAG UART
• Timer
• USB IP core (Encrypted form)

Many of you would be aware that Quartus Prime Pro's Platform Designer generates .ip files for components added in Platform Designer. These IP files shall be added in Quartus project.

In our top file, we instantiated Qsys (Platform designer) system and some other components.

Note that we have two components in encrypted form. We have Evaluation license available for USB IP core vendor. For C10GX family, Quartus license is not required.

As we were using evaluation license, Quartus was generating time limited SOF file. This is expected. So far, so good!

Issue:
For some debugging purpose, we commented out Qsys design instance from our top module. But we didn't remove .ip files related to this. With this, Quartus was unable to generate programming file and assembler report was showing following warnings:

Warning (115003): Can't generate programming files for your current project because you do not have a valid license for the following IP core or cores.
Warning (115005): Unlicensed IP: "Unknown(5750 0A40)"
Warning (115005): Unlicensed IP: "Nios II Embedded Processor Encrypted output(6AF7 00A2)"

Quartus synthesis report was showing following warnings:
Warning (18390): Intel FPGA IP Evaluation Mode (Simulation-Only) feature is turned on for all cores in the design
Warning (18394): Some cores in this design do not support the Intel FPGA IP Evaluation Mode feature
Warning (18395): "5750_0A40" does not support the Intel FPGA IP Evaluation Mode feature
Warning (18395): "Nios II Embedded Processor Encrypted output" does not support the Intel FPGA IP Evaluation Mode feature

This was strange as we already have evaluation license for that IP core and infact Quartus was showing that license in license menu.

Work-around:
We found out that if we remove encrypted IP core from design, we shall also remove its corresponding .ip files from Quartus project file list. With that, we were able to generate programming file again.

We hope this would be helpful to someone in future.

Thank you,
Bhaumik