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Valued Contributor III
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Waveform Editor - odd inversion

Hi, 

here is my code for a simple 8-bit counter with a decoded low signal for 1 clock period. 

 

 

 

signal Count: std_logic_vector(7 downto 0) := X"00"; 

if falling_edge(Bit_Clk_in) then 

Count <= std_logic_vector( unsigned(Count) + 1); 

end if; 

if Count(4 downto 0) = 24 then 

WritEn <= '0'; 

end if; 

if Count(4 downto 0) = 25 then 

WritEn <= '1'; 

write_address <= (write_address + 1) MOD 8; 

end if; 

 

 

 

I think this should produce a low pulse every 32 clock cycles but when I run a functional simulation in Waveform Editor the signal WriteEn is actually displayed as a single high going pulse. 

 

Has anybody else seen any thing like this? It is as if Waveform Editor has decided to invert the WriteEn signal for some reason 

 

any suggestions gratefully received 

PhilipJ
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Valued Contributor III
7 Views

 

--- Quote Start ---  

if Count(4 downto 0) = 24 then 

 

--- Quote End ---  

 

You're declaring a variable while evaluating it. 

I've never seen that.
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Highlighted
Valued Contributor III
7 Views

Can you post the exact source code?

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Highlighted
Valued Contributor III
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Sorry, I condensed my code so as not to take up too much space, which might have led it to be a bit confusing. 

 

I declare the variable Count as normal in 

 

architecture behavioral of <element> is 

signal Count: std_logic_vector(7 downto 0); 

... 

begin 

... 

if Count(4 downto 0) = 24 then 

.... 

end behavioral; 

 

The line you've highlighted is meant to simple take the bottom 5 bits of Count (it's an 8-bit counter) and see if it equal to '11000', I am still a relative novice with VHDL so please explain if I have misunderstood. 

 

regards 

PhilipJ
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Valued Contributor III
7 Views

 

--- Quote Start ---  

Can you post the exact source code? 

--- Quote End ---  

 

 

I hope I have attached the VHD file to this reply. 

Since originally posting, I think I have found that the problem was being caused by initialising variables, which caused Waveform Editor to get messed up in what it was drawing. 

I have now changed the VHD code to have an explicit NRESET input which forces all variables to their starting values and things are looking the way they are supposed to. 

 

regards 

PhilipJ 

edit: I've added the vwf file for the simulator as well (no I haven't 'cos the website thinks it' invalid :-(
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Valued Contributor III
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You are mixing incompatible libraries: 

use ieee.std_logic_unsigned.all; use ieee.numeric_std.all;  

You should only include one of them, but the first one is deprecated so you are left with the second. 

This will have the effect that you can no longer compare standard_logic_vector to an integer

So you either have to add more casts or switch to using unsigned in stead of std_logic_vector for counts etc. 

 

Using initial values should also work fine. Using a dedicated reset is, as you did, the other option to initialise the simulation. 

 

Regards, 

 

Josy
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Highlighted
Valued Contributor III
7 Views

 

--- Quote Start ---  

this should produce a low pulse every 32 clock cycles but when I run a functional simulation in Waveform Editor the signal WriteEn is actually displayed as a single high going pulse 

--- Quote End ---  

 

 

Perhaps you should replace the relational operator "equal" ( =24 ) by "less-or-equal" ( <=24 ).
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Highlighted
Valued Contributor III
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--- Quote Start ---  

Perhaps you should replace the relational operator "equal" ( =24 ) by "less-or-equal" ( <=24 ). 

--- Quote End ---  

 

 

You seem to be suggesting that this statement is "making Count take the value of 24", when I thought I was doing "if Count is equal to the value '24'". 

If I make it <=24 then it wont be a pulse that is low for one clock cycle it will be low as soon as Count is a value that is less than 24 i.e. when the counter rolls over from FF to 00 then WriteEn will be set to zero. 

 

I tried the 'C' type statement if Count == 24 but that was rejected by the Compiler so I thought I had got the correct statement as if Count = 24, perhaps that is my mistake... 

 

regards 

PhilipJ
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Valued Contributor III
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Hi, 

 

thanks for the advice about the libraries, I took out all the references to ieee.std_logic_unsigned.all whereupon all my if x = y statements failed so I then corrected them by casting my standard logic vectors to unsigned for the comparison. 

Perhaps the 'unsigned' library was producing something that then confused the simulator. 

 

As general advice, is it considered better to work with std_logic_vector or integer? I was originally trained in hardware logic design so working with std_logic_vectors (a 'bus' of binary signals) seem like the right thing to do but over the years the amount of 'C' programming has become dominant so working with integers in VHDL is very enticing!! 

 

Thanks for taking the time to help a VHDL beginner :-) 

regards 

PhilipJ
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Highlighted
Valued Contributor III
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--- Quote Start ---  

Hi, 

 

As general advice, is it considered better to work with std_logic_vector or integer? I was originally trained in hardware logic design so working with std_logic_vectors (a 'bus' of binary signals) seem like the right thing to do but over the years the amount of 'C' programming has become dominant so working with integers in VHDL is very enticing!! 

 

Thanks for taking the time to help a VHDL beginner :-) 

 

--- Quote End ---  

 

 

It happened the same way for me, as I started off with TTL circuitry back in the seventies, and I made the transition from std_logic_vector to unsigned/signed only a year or so ago, dabbling with integers first ... 

Unfortunately most VHDL textbooks focus on std_logic_vectors and integers. Integers look appealing but have their own peculiarities: they are usually limited to 32 bits, and if not constrained properly use 32 bits. With ieee.numeric_std unsigned and signed are a valid alternative. 

 

You're welcome! 

 

Regards, 

Josy
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