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Wavform Simulator Error: Invalid Licese Environment

yemo
Beginner
738 Views

I installed Quartus II 24.1 Lite Edition. When using waveform simulator, I found the error:

*** Running the ModelSim simulation **** c:/altera_lite/24.1std/questa_fse/win64//vsim -c -do test.do **

Fatal: Failed to initialize licensing environment. License environment not set correctly. Unable to checkout a license. Vsim is closing. ** Error: Invalid license environment. Application closing. Error.

Everything was fine before this error.

I have allready fixed my license to Quartus II in options-License Setup.Maybe my question is too basic to be answered but I have tried every method I could think about. Thank you.

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RichardTanSY_Intel
631 Views

Since you are using Quartus Lite, we have a quick start manual on how to run the Questa tool using the Nativelink simulation flow (only in Quartus Lite/Std edition).

You can download the example design and give it a run.

Once you are familiar with the simulation flow, try this with your own design and testbench.

https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html

 

Regards,

Richard Tan

 

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9 Replies
sstrell
Honored Contributor III
732 Views

Is your LM_LICENSE_FILE environment variable pointing to your license file?

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RichardTanSY_Intel
681 Views

 Questa Intel FPGA Edition Software required you to set up the LM_LICENSE_FILE environment variable.

You may checkout the user guide below on how to set up the Questa license.

https://www.intel.com/content/www/us/en/docs/programmable/683472/24-3-1/and-software-license.html


Regards,

Richard Tan


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yemo
Beginner
667 Views

LM_LICENSE_FILE environment variable is set correctly and I can see the simulation result but the output is unkonwn(XXXX).

 

ls138.v

module  ls138(G1,G2A,G2B,A,Y);
input   G1,G2A,G2B;
input  [2:0]  A;
output [7:0]  Y;
reg    [7:0]  Y;
always@(G1 , G2A , G2B , A)
 
begin
if(G1&&(!G2A)&&(!G2B))
begin
case (A)
3'b000:    Y<=8'b1111_1110;
3'b001:    Y<=8'b1111_1101;
3'b010:    Y<=8'b1111_1011;
3'b011:    Y<=8'b1111_0111;
3'b100:    Y<=8'b1110_1111;
3'b101:    Y<=8'b1101_1111;
3'b110:    Y<=8'b1011_1111;
3'b111:    Y<=8'b0111_1111;
default:   Y<=8'b1111_1111;
endcase
end
else     
Y<=8'b1111_1111;
end
endmodule

 

simulaotion result is attached.

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RichardTanSY_Intel
644 Views

Seem like a tool limitation with the Simulation Waveform Editor.


Try to run using our Questa Intel FPGA Starter Edition simulation tool. The tool should be able to provide the output data.


Regards,

Richard Tan


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yemo
Beginner
633 Views

 Can you explain the process in detail?

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RichardTanSY_Intel
632 Views

Since you are using Quartus Lite, we have a quick start manual on how to run the Questa tool using the Nativelink simulation flow (only in Quartus Lite/Std edition).

You can download the example design and give it a run.

Once you are familiar with the simulation flow, try this with your own design and testbench.

https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html

 

Regards,

Richard Tan

 

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RichardTanSY_Intel
450 Views

Any update on this?


Do you able to simulate using the Questa Intel FPGA Starter Edition?


Regards,

Richard Tan


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yemo
Beginner
421 Views
Sorry, something occurred these days and it took all mind. My problem is solved and thank you for your patience and notice.
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RichardTanSY_Intel
401 Views

Thank you for acknowledging the solution provided. I'm pleased to know that your question has been addressed. 


Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.


Thank you and have a great day!


Best Regards,

Richard Tan



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